My Day at the IBM Partner Summit
May 15, 2012
3D InCites
Want to know how to torture a journalist? Invite them to present at a conference but ask them to sign an NDA so they can’t write about it! However, I can say this much: the 3D Program is alive and well at IBM. From IBM Fellow, Subramanian Iyer, I learned some basic truths about scaling and 3D. One of the current challenges being faced where 3D can provide the solution is in the power budget. Communication between chips can take up to a third of the system power. “Semiconductor scaling doesn’t address this issue, but tighter inter-chip connections can,” notes Iyer. “3D does not eliminate the need to scale, it’s an orthogonal element for increasing performance.” He added that the cost per transistor still needs to come down.

Moore’s Law: Wanted, Dead or Alive
May 14, 2012
EDA360
Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held on April 26 at the Computer History Museum in Mountain View, California. Iyer pointed out that process complexity has grown from node to node. Yes we already knew that—but in earlier node transitions the increased processing cost was offset by the doubled number of additional transistors per unit area you get for each jump. Iyer projected a graph showing that the reduced effective cost per transistor stops falling after the 32/28nm node.

Bozotti has a dream: to turn round ST's digital problem
May 10, 2012
EE Times
GENEVA Switzerland – Carlo Bozotti, CEO of European chip company STMicroelectronics NV, has a dream. It is to have both sides of his company be successful and that means fixing mobile chip joint venture ST-Ericsson. Bozotti was interviewed on stage at an executive conference organized here by the Global Semiconductor Alliance (GSA) industry trade group. His inquisitor was GSA chairman Joep van Beurden, who is also CEO of fabless wireless chip company CSR plc. Bozotti told van Beurden, and through him and audience of senior semiconductor executives, that ST will do "whatever it takes," to fix the problem.

True 3D MEMS Work at MIT Takes MEMS beyond Quasi-3D
May 07, 2012
EE Journal
Everyone is jumping on the 3D bandwagon. But if I said that MEMS was just taking some steps in that direction, you might understandably question my mental health, since, at first blush, it would seem that MEMS structures are already 3D. After all, that most primitive MEMS element, the cantilever, to name one example, is specifically intended to move out of the wafer plane – why is that not 3D?

Getting down to the Business of 3D ICs
May 02, 2012
3D InCites
Really, it all boils down to simple economics. I'm referring to WHY the road to 3D is taking as long as it is to reach commercialization. We've convinced the engineers of the technology benefits. Now it's time to convince those who hold the purse strings: the management. I had an interesting discussion about this with Herb Reiter upon his return from Tokyo where he moderated a 3D panel at the GSA/SEMATECH Memory+ Conference there. He said while there were no "Aha!" moments to report, the message clearly conveyed by the panelists was that the design and manufacturing companies are committed to playing their position in the 3D ecosystem.

Keeping Moore's Law Alive
April 30, 2012
SemiWiki.com
From Silicon Summit 4/26/12 At the GSA silicon summit yesterday the first keynote was by Subramanian Iyer of IBM on Keeping Moore's Law Alive. He started off by asking the question "Is Moore's Law in trouble?" and answered with an equivocal "maybe." Like some of the other speakers during the day, he pointed out that 28nm will be a long-lived process, since the move to 20nm is not really that compelling (for instance, despite Intel's $12B investment, comparing Sandy Bridge and Ivy Bridge there is a 4% reduction in power for roughly the same performance).

GSA 3DIC and Cadence
April 29, 2012
SemiWiki.com
At the GSA 3D IC working group meeting, Cadence presented their perspective on 3D ICs. Their view will turn out to be important since the new chair of the 3D IC working group is going to be Ken Potts of Cadence. Once GSA decided the position could not be funded then an independent consultant like Herb Reiter had to bow out and the position would need to be taken by someone funded by the company they work for. So thanks Cadence. And thanks for the beer and wine after the meeting too.

A Modeling Approach for Power Integrity Simulation in 3D-IC Designs
April 27, 2012
EE Times Design
Designing reliable three-dimensional (3D) system-on-chips (SoCs) is extremely complex, and critical for the next level of integration in silicon design. In 3D integrated circuit (3D-IC) vertical stacked-die architecture, individual die are connected directly by Through-Silicon-Vias (TSVs) and micro-bumps. Simulation of 3D-ICs for power integrity needs to model the 3D structure, including all the ICs and their TSV interconnects. Some challenges include modeling and integrating third-party application SoCs or memories into the current design framework and performing a complete analysis. This article outlines an approach for concurrent analysis of the 3D-IC power grid, as well as a chip model-based analysis, and how analysis based on a chip macro-model can yield the same results as concurrent full-chip analysis, resulting in significant runtime benefits.

A modeling approach for power integrity simulation in 3D-IC designs
April 27, 2012
EE Times
Abstract Designing reliable three-dimensional (3D) system-on-chips (SoCs) is extremely complex, and critical for the next level of integration in silicon design. In 3D integrated circuit (3D-IC) vertical stacked-die architecture, individual die are connected directly by Through-Silicon-Vias (TSVs) and micro-bumps. Simulation of 3D-ICs for power integrity needs to model the 3D structure, including all the ICs and their TSV interconnects. Some challenges include modeling and integrating third-party application SoCs or memories into the current design framework and performing a complete analysis. This article outlines an approach for concurrent analysis of the 3D-IC power grid, as well as a chip model-based analysis, and how analysis based on a chip macro-model can yield the same results as concurrent full-chip analysis, resulting in significant runtime benefits.

Professor Chenming Hu talks FinFETs and FDSOI at the GSA Silicon Summit
April 26, 2012
EDA360
Chenming Hu, TSMC Distinguished Chair Professor of Microelectronics at University of California at Berkeley gave a keynote talk on FinFETs and FDSOI (fully depleted silicon on insulator) today at the GSA Silicon Summit held at the Computer History Museum in Mountain View, California. The talk was a somewhat abbreviated version of the talk he gave last year at Cadence. Rather than rewriting the blog, I invoke the mighty powers of the Web Hyperlink. You can see what the Professor said today (and last year) by clicking here:

3D Thursday: Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products”
April 26, 2012
EDA360
Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including wafer fab process nodes, backend interconnect, and packaging technologies. He opened his talk by discussing the Qualcomm Snapdragon series of mobile application processors (see “Qualcomm renames existing ARM-based Snapdragon mobile application processors and provides future roadmap”). Qualcomm Snapdragon processor chips combine one to four 32-bit RISC processor cores with a GPU, display controller, sound subsystem, and various I/O interfaces. All of these IP blocks go onto one 2D die but Qualcomm can’t afford to stop there. There’s more to a mobile phone handset than an applications processor. You’ll also find chips for RF, memory, power control, and sensors. “We need 3D because all of this is out of the question [in monolithic 2D form],” said Yu.

3D Thursday: GLOBALFOUNDRIES adds TSV capability for 28nm and 20nm die to Fab 8 in Saratoga County, New York
April 26, 2012
EDA360
Customers’ clamor for 3D IC assembly capability and die with TSVs (through-silicon vias) has apparently gotten loud enough to cause a change of game plan for GLOBALFOUNDRIES, which announced today that it is spending “tens of millions of dollars” to add TSV-making capability to its production line at the company’s Fab 8 facility in Saratoga country, New York. In fact the announcement was of sufficient import for Subramani Kengeri—GLOBALFOUNDRIES’ head of Advanced Technology Architecture in the office of the CTO—to note today’s announcement in his morning keynote address at the GSA Silicon Summit at the Computer History Museum in Mountain View, California. GLOBALFOUNDRIES will use the equipment to add TSVs to 28nm and 20nm die. The company expects that the first full-flow silicon with TSVs will start running at Fab 8 in Q3, 2012.

SEMATECH Technologists Demonstrate Breakthrough Process Solutions for Extending Advanced Memory and Logic Technologies
April 25, 2012
Business Wire
HSINCHU, Taiwan, Apr 25, 2012 (BUSINESS WIRE) -- SEMATECH experts reported on innovative approaches to realize advanced CMOS logic and memory device technologies and 3D through-silicon via (TSV) manufacturing at the International VLSI Technology, System and Applications Symposium (VLSI-TSA) on April 23-25, 2012.

MonolithIC 3D Inc. Issued Patents on 3D-IC Logic, Memories and Micro Display
April 25, 2012
PRWeb
MonolithIC 3D Inc., a Silicon Valley startup, announced today that the USPTO has issued MonolithIC 3D three additional patents on monolithic 3D IC, 3D logic and integration with image sensor or micro display, and 3D Memories. This milestone increases the company’s portfolio of issued patents from 7 to 10 over the previous ten months. These issued patents are joined by over 50 pending applications. This makes the company one of the key players in the 3D-IC field. On the company’s webpage you can find the complete list of issued patents and details about the innovative technology it provides.

New Dimension in Chips What 3D ICs Mean for the FPGA Industry
April 17, 2012
Electronic Engineering Journal
3D is one of the hottest buzzwords these days. Every marketeer worth his salt is trying to find a way for the next “new thing” to be plausibly labeled as “3D.” 3D is cool. We see it in movies. The bad guys jump right out from the screen. 3D is real, vibrant, and immersive. 2D is, well, flat and boring.

IFTLE 97 DATE in Dresden, Synopsys 3D EDA Solution
April 15, 2012
Solid State Technology
ARM, IMEC and the Swiss Federal Institute of Technology (EPFL) gave an interesting presentation on the "Performance and Efficiency of 3D Stacked DRAM in a Multicore System." The goal of this 2010 - 2012 European commission funded project, known as "Euro Cloud," is to integrate ARM processor cores with 3D DRAM for very dense, low power data centers for mobile cloud services for hand held devices. Coupling of high performance ARM Cortex processors with 3D memory is targeting the mobile cloud services from Nokia which will serve millions of "mobile handsets." Their analysis shows that although 3D-stacked DRAM, such as Wide-IO, allow for wider buses by providing increased pin density, the wider buses saturate in providing additional throughput. The authors propose that rather than increasing the width, more channels that are effectively managed by memory controllers lead to increased overall system performance. They also conclude that 2.5D is preferable to 3D for systems with challenging thermal performance.

Abu Dhabi, Saxony Invest in 'Twin Labs' 3-D IC Project
April 13, 2012
EE Times
Advanced Technology Investment Co. (ATIC), the majority owner of foundry chipmaker Globalfoundries Inc. (Milpitas, Calif.), and the State of Saxony in Germany have agreed to invest $4.8 million in twinned laboratories that will research 3-D stacking of integrated circuits.

Georgia Tech Targets Thin 3D Packaging with New Consortium
April 11, 2012
Advanced Packaging
Georgia Institute of Technology (Georgia Tech) Packaging Research Center (GT-PRC) proposes a new consortium on 3D semiconductor packaging called 3D ThinPack (THInPack) for ultra-miniaturized 3D heterogeneous, RF, digital and power modules in partnership with global companies.

Panelists: What Needs to Happen for 3D-IC TSV Success
April 11, 2012
Cadence Blog
It's time to get to work if we want to bring 3D-ICs with through-silicon vias (TSVs) into the semiconductor design mainstream. What ecosystem support is needed in the short term, medium term, and long term to make this new technology successful? That's the question that was put to a panel of 3D-IC experts at the recent Electronic Design Processes Symposium (EDPS) April 6, 2012 in Monterey, California.

IBM analytics to plumb universe's secret
April 09, 2012
EE Times Asia
IBM will harness water-cooled 3D chip sets to plumb the secrets of the universe by analyzing exabytes (billion gigabytes) of data streaming in from the world's largest radio telescope to be constructed in 2024.

EDA Symposium: Users Cite 3D-IC Design Tool Needs
April 09, 2012
Cadence Blog
What's needed to bring 3D-ICs with through-silicon vias (TSVs) - or 2.5D ICs with silicon interposers - into the IC design mainstream and volume production? That question resonated through a day-long session on 3D-ICs at the Electronic Design Processes Symposium (EDPS) April 6, 2012 in Monterey, California.

Synopsys Users Group 2012 Keynote: Dr Chenming Hu and Transistors in the Third Dimension!
April 08, 2012
SemiWiki.com
t was an honor to see DR. Chenming Hu speak and to learn more about FinFets, a technology he has championed since 1999. Chenming is considered an expert on the subject and is currently a TSMC Distinguished Professor of Microelectronics at University of California, Berkeley. Prior to that he was the Chief Technology Officer of TSMC. Hu coined the term FinFET 10+ years ago when he and his team built the first CMOS FinFETs and described them in a 1999 IEDM paper. The name FinFET because the transistors (technically known as Field Effect Transistors) look like fins. The fins are the 3D part in the name 3D transistors. Dr. Hu didn’t register patents on the design or manufacturing process to make it as widely available as possible and was confident the industry would adopt it, and he was right.

Visiting the Valley in 3D
April 05, 2012
3D InCites
Some people get excited when they go to Hollywood and see famous people. Not me. Today, I got positively giddy driving from from San Jose airport to both Invensas and Ultratech’s headquarters. Oh look! It’s SAMSUNG R&D CENTER! Toshiba! MICRON! I felt that I was in the presence of greatness. Yes – my inner geek is showing. But most of the time I’m working from my home in Arizona, just reading about all these places. Coming to Silicon Valley every once in a while gives me a chance to visit with the people who make this industry hum and become inspired to write about what I learn.

MarketsandMarkets: Global 3D IC and TSV Interconnect Market worth $6.55 Billion by 2016 Read more here: http://www.sacbee.com/2012/04/04/4389658/marketsandmarkets-global-3d-ic.html#storylink=cpy
April 04, 2012
the Sacramento Bee
DALLAS, April 4, 2012 -- /PRNewswire/ -- According to a new market research report "Three-dimensional Integrated Circuit (3D IC/Chip) & Through-Silicon Via (TSV) Interconnects Market - Global Forecast & Trend Analysis (2011 - 2016) By Technology (Substrate, Bonding Techniques, Process Realization, Fabrication), Products (Memory, LED, Sensor, MEMS, Power & Analog Components) & Applications (Mobile Devices, Processors, ICT, Networking, Automotive, Defense)" published by MarketsandMarkets (http://www.marketsandmarkets.com), the total 3D IC market is expected to reach $6.55 billion by 2016 at a CAGR of 16.9% from 2011 to 2016. Read more here: http://www.sacbee.com/2012/04/04/4389658/marketsandmarkets-global-3d-ic.html#storylink=cpy

Interposer Ecosystem Examined
April 01, 2012
Advanced Packaging
At the recent IMAPS Device Packaging Conference in Ft. McDowell, AZ, Solid State Technology's Insights from the Leading Edge (IFTLE) brought together a panel of manufacturers, users and market specialists to discuss the evolving 2.5D / 3D Infrastructure.

Advanced Packaging in the New Decade
April 01, 2012
Advanced Packaging
In the last decade, advanced packaging has emerged as an enabler of today’s electronic products. The impact of packaging, assembly, and test is increasingly felt in the semiconductor industry and package selection is important to the success of the end product. The industry has seen a package evolution in the past 10 years and the road ahead may require a package revolution.

Packaging Players Face High Stakes
March 30, 2012
Printed Circuit Design & Fab
Two poker games occurred at the IMAPS Global Business Council and International Device Packaging Conference held in Ft. McDowell, AZ, in early March. One was a game of Texas Hold’em for attendees; the other had much bigger stakes. Time was, companies were vertically integrated, and large semiconductor companies established and maintained assembly operations to produce packages. While a few companies, including IBM, Intel, Samsung, Texas Instruments and others, maintain strategic assembly operations, many companies shifted to the “asset light” model, and the era of the fabless semiconductor emerged. The industry is potentially entering a new stage with the move to 2.5D (chips mounted on silicon interposers) and 3D with through silicon vias (TSVs). Will the fabless model still produce the high margins of the past? Is the industry moving back to its past with a new vertical integration infrastructure?

Amkor Licenses 3D Packaging Tech to SHINKO
March 30, 2012
Advanced Packaging
Semiconductor packaging and test services (SATS) provider Amkor Technology Inc. (NASDAQ:AMKR) granted SHINKO ELECTRIC INDUSTRIES CO., LTD. (Tokyo:6967) a non-exclusive license to its proprietary Through Mold Via (TMV) semiconductor packaging technology.

Micron Advances with 3D Chips
March 28, 2012
EE Times Asia
Micron Technology Inc. has revealed that it is adding new supporters and specifications with regard to its planned release of the Hybrid Memory Cube in 1H13, an ultra-dense memory device. The move by the company is in response to the increasing interest surrounding 3D chip ICs.

2.5D ICs are more than a stepping stone to 3D ICs
March 27, 2012
EE Times
With Xilinx releasing last year the first commercially available 28nm, 2.5D Stacked Silicon Interconnect (SSI) device (the Virtex-7 2000T FPGA) followed by TSMC announcing full manufacturing and assembly support for 2.5D and 3D IC designs, the rest of the IC industry is starting to rev up efforts to make 2.5D and eventually 3D IC technology a mainstream reality.

Synopsys: now in 3D
March 26, 2012
SemiWiki.com
And no red and green glasses required. I remember the first time I heard about a Through Silicon Via (TSV), punching a hole through the entire wafer to make an electrical connection at the back, like we do all the time in printed circuit boards with through plated holes. I thought someone was trying one on and trying to make me look a fool. But it is real and becoming realer (as my daughter used to say).

Synopsys Unveils 3D-IC Initiative
March 26, 2012
EE Journal
Comprehensive EDA Solution to Enable Design of Stacked Multi-Die Systems Using TSV and Silicon Interposer Technologies MOUNTAIN VIEW, Calif., March 26, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today unveiled its initiative to accelerate the design of stacked multiple-die silicon systems using 3D-IC integration to meet the requirements of faster and smaller electronic products that consume less power. As part of its 3D-IC initiative, Synopsys is working closely with leading IC design and manufacturing companies to deliver a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.

TSMC, Altera Team on 3-D IC Test Vehicle
March 22, 2012
EE Times
Claiming an industry first, foundry Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and programmable logic vendor Altera Corp. Thursday (March 22) announced the joint development of a heterogeneous 3-D IC test vehicle using TSMC's chip-on-wafer-on-substrate integration process.

Surprise! Altera and TSMC develop heterogeneous 3D IC test vehicle
March 22, 2012
EE Times
Eeek alors! The net is buzzing with the news that the folks from Altera and TSMC have just announced their joint development of what they describe as “The world’s first heterogeneous 3D IC test vehicle using TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process” (see also Dylan McGrath’s column TSMC, Altera team on 3-D IC test vehicle).

Scaling the 20nm peaks to look at the 14nm cliff, Part 1: Tom Beckley from Cadence maps the challenges of advanced node design at ISQED
March 21, 2012
EDA360
Yesterday at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote that lays out the challenges for IC designers tackling advanced node designs at 20nm and below. The room at ISQED was filled with a couple of hundred people and did they ever get an earful. Beckley’s team of 800 EDA developers has been working closely with customers to get the kinks out of 20nm design and has also started down the path to 14nm. Lessons learned from these early 20nm designs fueled Beckley’s talk, titled “Taming the Challenges of Advanced-Node Design.”

Glass vs. Silicon Interposers for 2.5D and 3D IC Applications
March 20, 2012
EDA360
There has been enough interest stirred up in R&D around glass as a low-cost alternative interposer substrate material compared with silicon, that there was an entire session dedicated to developments in that area at the 2012 IMAPS International Device Packaging conference, held March 5-8 in Scottsdale, AZ.

3D Thursday: 3D ICs and analog chips. Where’s the match? Is there a match?
March 20, 2012
EDA360
Dr. Venu Menon, VP of Analog Technology Development at TI, gave a deeply informative lunchtime keynote speech at this week’s ISQED Symposium. Most of Menon’s presentation discussed analog process technology: what’s important to analog chip design and manufacturing, what’s changed over the years, what are the differences between analog and digital IC processes, etc. However, one slide in particular caught my eye as a perfect topic for this week’s 3D Thursday.

TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”
March 14, 2012
Cadence Blog
The world's largest foundry provider, TSMC, is confident it can keep up with the semiconductor scaling predicted by Moore's Law and can even outpace Moore's Law through 2.5D and 3D-ICs. It's all part of the "incredible high-tech future" predicted by Rick Cassidy, president of TSMC North America, in a keynote speech at CDNLive! Silicon Valley (Cadence user conference) March 13, 2012.

Shin-Etsu Chemical Joins EVG Wafer Bonding Supply Chain
March 14, 2012
Advanced Packaging
EV Group (EVG), semiconductor and MEMS fab equipment supplier, welcomed semiconductor materials supplier Shin-Etsu Chemical Co. Ltd. into its open platform for temporary bonding/debonding (TB/DB) materials supporting 3D semiconductor packaging. Shin-Etsu will work with customers to commercialize 3D IC packaging via wafer bond/debond in volume manufacturing environments.

Cadence TSMC, ARM call for more collaboration
March 13, 2012
EE Times
SAN JOSE, Calif. – Electronics companies need to step up their collaboration to deal with growing complexity of the technology, said executives from Cadence, TSMC and ARM at an annual Cadence user event here. “Silicon integration and complexity will be a real challenge,” said Lip-Bu Tan, chief executive of Cadence, noting 20 nm chips with eight billion transistors in the works.

Wide I/O driving 3-D with TSV
March 09, 2012
EE Times Asia
The standard for Wide I/O mobile DRAM, released by Jedec in January, uses through-silicon vias (TSVs) to connect DRAM to logic on three-dimensional integrated circuits. With its 512bit data interface, JESD229 Wide I/O Single Data Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.

Applied Materials, IME open Singapore 3-D packaging lab
March 07, 2012
EE Times
LONDON – Applied Materials, the largest producer chipmaking equipment, and Singapore's Institute of Microelectronics have officially opened a center for advanced packaging at Science Park II in Singapore.

The future of computers: 3D chip stacking
March 07, 2012
Extreme Tech
In a few weeks, Intel will release Ivy Bridge, the first mass-produced 22nm parts, and more importantly the first to use 3D “tri-gate” FinFET transistors. These CPUs will be incredibly fast and use very little power, but ultimately they are just another last-gasp effort to squeeze a little more life out of a material and process that will soon hit a wall. Computing is still predominantly single-threaded; throwing more transistors and more cores at a problem will only take you so far.

EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More
March 05, 2012
Cadence Blog
What's driving the EDA industry today and where is it headed in the near future? Some high-level answers to these questions came from the EDA Consortium (EDAC) annual CEO Forecast panel Feb. 29, 2012. EDA industry leaders shared their views about 3D-ICs, SoC integration, power management, industry growth drivers, the structure of the EDA industry, and the geographical location of design work 5 years out.

MonolithIC 3D Inc. Issued Patents on 3D FPGAs and 3D Memories
February 29, 2012
PRWeb
MonolithIC 3D Inc., a Silicon Valley startup, announced today that it has been issued fundamental patents on 3D Field Programmable Gate Arrays (FPGAs) and 3D Memories. The company now has 7 issued patents with more than 50 other patents pending, making it one of the key players in the 3D-IC field. MonolithIC 3D Inc. was recently selected as a Finalist of the “Best of Semicon West 2011” for its disruptive technology.

3D processor-memory mashups take center stage
February 24, 2012
The Register
ISSCC A trio of devices that stack layers of compute units and memory in a single chip to boost interconnect bandwidth were presented at this week's International Solid-State Circuits Conference in San Francisco.

Wide I/O driving 3-D with through-silicon vias
February 22, 2012
EE Times
The standard for Wide I/O mobile DRAM, released by Jedec in January, uses through-silicon vias (TSVs) to connect DRAM to logic on three-dimensional integrated circuits. With its 512-bit data interface, JESD229 Wide I/O Single Data ­Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.

Challenges, Opportunities of the 2.5D/3D Ecosystem
February 13, 2012
EE Times Asia
For decades, Moore's law has predictably driven Silicon scaling, and, semiconductor manufacturing has been based largely on planar (2D) technology. The 2D design and manufacturing sequence has had its clearly defined phases: specification, design, fabrication, assembly and test. Each phase is a well-defined function with understood borders between each other. As the semiconductor manufacturing world moves into the "More than Moore" 2.5D/3D space, a wealth of opportunities are becoming available that further increase the functionality and performance of semiconductor ICs.

Viewpoint: How will the chip wars be won? -- Part 1
February 08, 2012
EE Times
A changing silicon landscape For nearly four decades, silicon technology development has been shaped primarily by the growth of the personal computing industry and the need to continuously increase the performance of digital transistors. Over the years, transistors have continually become smaller, faster and cheaper in line with Gordon Moore’s observation that accurately predicted the era of CMOS scaling.

High-Performance, Cost-Effective Heterogeneous 3D FPGA Architectures
February 03, 2012
Brown University
ABSTRACT In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a novel design partitioning methodology that maps the heterogeneous computational resources of an FPGA into a number of die such that the total die area is minimized and the FPGA performance is maximized.

Advances in 3D-IC Testing
February 03, 2012
EE Times Asia
Three-dimensional integrated circuit (3D-IC) systems has the potential to provide significant improvements in performance, power, functional density, and form factor over other packaging integration techniques. Despite substantial progress toward realizing 3D-IC systems, a variety of design, manufacturing, packaging, and testing issues still need to be addressed before cost-effective, high-volume production can be achieved. In this article we will focus on the test challenges and solutions, highlighting a design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute (ITRI) based on the Synopsys test solution.

TSMC plans 3-D IC assembly launch early in 2013
February 02, 2012
EE Times
Leading IC foundry Taiwan Semiconductor Manufacturing Co. Ltd. plans to announce 3-D IC assembly service as a general offering at the beginning of 2013, according to Maria Marced, president of TSMC Europe.

3-D IC Standards Needed Within Six Months
February 01, 2012
EE Times Europe
Standards for 3-D chip stacks need to be in place within six months to stay ahead of chips rolling out in 2013, said a Qualcomm executive driving some of the efforts.

CEA-Leti Opens 3-D IC Packaging Service
February 01, 2012
EE Times
French research institute CEA-Leti has announced the launch of a 3-D packaging platform and service that provides industrial and academic partners with what it describes as a "mature" process for the production of 3-D interconnected products and projects.

Metallization Processes for Standardized Wide-IO Memory Applications
January 26, 2012
Advanced Packaging News
Expensive vacuum-based, dry-process tools developed for sophisticated dual-damascene applications are not the fittest solution for the manufacturing of TSVs for 3D-IC applications.

3D Integration: Not a Windfall for Test
January 19, 2012
Advanced Packaging News
After a seemingly interminable run of being “a year away,” it is clear that 3D integration (or at least the silicon-interposer-enabled 2.5D version) now offers a viable path to achieve the performance, cost, and feature integration required of next-generation mobile devices. As with any significant shift in process technology, a redistribution of the value provided by different semiconductor supply-chain elements is likely here, along with a corresponding shakeup of the winners and losers in the supply chain.

12-in Wafer Bonding Machine for 3D LSI ICs Developed
January 17, 2012
EE Times Asia
Mitsubishi Heavy Industries Ltd (MHI) has developed what it claims as the world's first fully automated 12-inch (300mm) wafer bonding machine that is capable of producing 3D integrated large-scale integration (LSI) circuits at room temperature.

3-D Chips Grow Up
January 16, 2012
IEEE Spectrum
The integrated circuit could use a lift. Almost 50 years after Gordon Moore forecast the path toward faster, cheaper chips, we've miniaturized electronic components so much that we're increasingly colliding with fundamental physical limitations. The days of simple transistor scaling are long behind us—the latest, greatest chips are a hodgepodge of materials and design tweaks. These chips also leak a lot of power, and they contain transistors that are so variable in quality they're difficult to run as intended.

Sematech to Assess 3-D Tools for Volume Production
January 16, 2012
EE Times
Sematech is preparing to assess how 3-D tools can be tuned for high-volume manufacturing needs.

The Fast Track to 3D-IC Testing
January 16, 2012
EE Times
Three-dimensional integrated circuit (3D-IC) systems offer the potential to deliver significant improvements in performance, power, functional density, and form factor over other packaging integration techniques.

IFTLE 85 2.5/3D Headlines at the 2011 RTI ASIP
January 15, 2012
Advanced Packaging News
Research Triangle Institutes 3-D Architectures for Semiconductor Integration and Packaging Conference, or 3D ASIP (as it has become known) normally finishes off the '3D conference circuit' for the year and is a good gauge of how far things have progressed in the last 12 months. At the 7th 3D ASIP in Burlingame CA a few weeks ago, there were several announcements, statements and rumors having significant impact on the 2.5/3D community.

Semiconductor Packaging Houses Gain From More Device Complexity
January 11, 2012
Advanced Packaging News
Increased I/O density on chips, power/performance requirements, yield/cost requirements and form factor constraints (mobile) are coming to push increased use of flip chip, 2.5D and 3D technologies. This trend benefits the packaging subcontractors in the semiconductor industry, argues Credit Suisse Taiwan Analyst Randy Abrams, as outsourcing rises.

3D Integration Key to 22nm Semiconductor Devices
January 02, 2012
Advanced Packaging News
3D IC integration techniques offer many benefits, the most notable being smaller footprint, lower power and higher bandwidth. From a cost standpoint, 3D’s biggest advantage is the ability to partition large, complex dies into smaller functional blocks. This improves yield and manufacturing cost equations, and enables testing/replacement of semiconductor dies prior to integration. Furthermore, individual functional blocks enable a modular design with standardized components, e.g., an ASIC manufacturer can focus on developing the ASIC and combine it with off-the-shelf memory. This allows significant reductions in complexity and cost for design and test.

TSMC Repeats Call for Foundry-centric 2.5/3D Industry
December 29, 2011
Advanced Packaging News
At the recent 7th annual RTI 3-D Architectures for Semiconductor Integration and Packaging (3D ASIP) Conference in Burlingame CA, the "buzz" centered around the presentation by TSMC's Doug Yu, senior director of integrated interconnect, who repeated the case he had made at the November Georgia Tech Interposer Conference [see "2.5D announcements at the Global Interposer Tech conference"] for the pure foundry model for 2.5 and 3DIC -- claiming that TSMC was readying to take on full beginning to end interposer manufacturing.

GSA Publishes 3D/2.5D Packaging Studies
December 27, 2011
Advanced Packaging News
The Global Semiconductor Alliance (GSA) released "3D IC Architecture: A Natural Evolution," a report sponsored by Macronix International Co. Ltd. and Etron Technology Inc. GSA also published the second edition of the 3D IC Design Tools and Services Tour Guide

Rambus, ITRI Team Up for 3D Packaging
December 20, 2011
EE Times Asia
Rambus Inc. has announced that it is partnering with the Industrial Technology Research Institute (ITRI) in Taiwan on the development of interconnect and 3D packaging technologies. The licensing company has stated that it will work with the research institute on the development of system integration using silicon interposer technology.

First 3-D IC Spec Set for Release
December 16, 2011
EE Times
JEDEC which announced a broad set of 3D IC standards development earlier in 2011 is all set to release what is touted as the first 3D IC interface standard which will be out in late December of this year (or some time in January 2012).

Rambus, ITRI to Collaborate on 3-D Packaging
December 15, 2011
EE Times
Technology licensor Rambus Inc. said Wednesday (Dec. 15) it is engaging Taiwan's Industrial Technology Research Institute (ITRI) on the development of interconnect and 3-D packaging technologies.

TSMC Goes it Alone with 3-D IC Process
December 13, 2011
EE Times
TSMC will try to go it alone with an integrated 3-D chip stacking technology as its only offering for future customers. The approach makes commercial sense for TSMC, but some fabless chip designers said it lacks technical merit and limits their options.

Test Challenges and DFM Debate Seen in 3D Chip Era
December 13, 2011
SemiMD
As the industry has lowered its chip-testing costs over the years, IC test has been somewhat predictable. But in the emerging 2.5D and 3D chip era, IC test is entering the spotlight and the traditional test flow is under the gun.

Si2 Announces Founding Members of the Open3D Technical Advisory Board
December 08, 2011
Company Press Release
The Silicon Integration Initiative (Si2) announced today the founding members of their Open3D Technical Advisory Board (TAB), which is chartered to enable interoperable 2.5D and 3D design flows with open standards, providing common formats and interfaces.

Fast Forward: Finding New Common Ground in Process Technology R&D
December 06, 2011
SEMI
The structural evolution our industry over the last decade has heightened the need for collaboration, and the semiconductor community has responded by developing new ways to work together on major transitions in device structures, patterning, materials, and manufacturing. Projecting forward five years, as we push into the sub 14nm realm, how will our collaborations change, as we tackle difficult challenges such as heterogeneous packaging, 3D device structures, nanodefectivity, and 450mm?

TSMC Gearing Up for Via-First TSV
December 05, 2011
DIGITIMES
While major IC packagers have already devoted resources on TSV (via-last) development, Taiwan Semiconductor Manufacturing Company (TSMC) is also eyeing the market with its front-end process (via-first).

IBM, Micron to Produce 3D Memory Chips
December 05, 2011
EE Times
IBM and Micron Technology announced that Micron will begin production of new hybrid memory cube (HMC) device built using the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs)—IBM's 3D chip-making process.

TSMC Gearing Up for Via-First TSV
December 05, 2011
DIGITIMES
While major IC packagers have already devoted resources on TSV (via-last) development, Taiwan Semiconductor Manufacturing Company (TSMC) is also eyeing the market with its front-end process (via-first).

Transistor Wars Rival architectures face off in a bid to keep Moore's Law alive
November 18, 2011
IEEE Spectrum
Illustration: David Plunkert In May, Intel announced the most dramatic change to the architecture of the transistor since the device was invented. The company will henceforth build its transistors in three dimensions, a shift that—if all goes well—should add at least a half dozen years to the life of Moore's Law, the biennial doubling in transistor density that has driven the chip industry for decades.

Sematech Starts 3D Tech Forum
November 09, 2011
EE Times Asia
Sematech Inc. has initiated a centralized online forum, the 3D Standards Dashboard, for members of the 3D interconnect community. The forum will be a platform for the community to discuss and exchange information on standards activities.

3D-IC: Ushering in a New Era in the Semiconductor Industry
November 09, 2011
SEMI
Semiconductor packaging technology has transformed from 2D into 3D stacking. Currently, the industry is working on materials, equipment, manufacturing and product standardization to achieve technology optimization, time-to-market expedition and cost reduction. Twenty-five industry executives shared their viewpoints at the “SiP Global Summit” held by SEMI in Taiwan. The three-day event attracted around 1,060 attendees from the industry.

Invensas Acquires ALLVIA 3D-IC Packaging Technology
November 02, 2011
PCBCafe
Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc. (Nasdaq: TSRA), announced today that it has acquired the patent assets of ALLVIA, Inc. In addition, Invensas has entered into a two-year collaborative partnership with ALLVIA to further develop technology and intellectual property (IP) in the 3-dimensional integrated circuit (3D-IC) packaging space.

Chip Makers Intensify Race in 3D DRAM Market
October 15, 2011
SemiMD
The 3D DRAM race is heating up, as more companies are teaming up to share the costs and accelerate the development of the technology.

ST Rolls MEMS Using TSV
October 14, 2011
EE Times India
STMicroelectronics claims to be the world's first manufacturer to have implemented Through-Silicon Via technology (TSV) in high-volume MEMS production.

Perfecting the 3-D Chip
October 12, 2011
EE Times
You've heard the hype: The foundation of semiconductor fabrication will be transformed over the next few years as multistory structures rise up from dice that today are planar.

R&D Group Begins TSV Chip Pilot Production
October 11, 2011
EE Times
All Silicon System Integration Dresden (ASSID), a microelectronics wafer-level packaging and system integration center backed by the government of the German state Saxony and operated by the Fraunhofer IZM Institute, has begun pilot-line production of 3-D semiconductor devices with through-silicon-vias (TSVs), according to a statement issued Monday (Oct. 10) by one of its suppliers, Altatech Semiconductor SA.