GSA's mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective fabless ecosystem through collaboration, integration and innovation. GSA addresses industry challenges by collaborating to remove the hurdles that hamper semiconductor growth and by encouraging the growth in the supply chain.

Through the formation of our Supply Chain Interest Groups, GSA:

• Provides a platform for meaningful global collaboration
• Identifies and articulates market opportunities and solves industry challenges
• Provides members with comprehensive and unique market intelligence
• Encourages and supports entrepreneurship

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With the invention of the transistor by Bell Labs in 1947, the semiconductor industry has grown to a $257 billion industry, with fabless companies representing $53 billion of that. In 2008, the industry was comprised of more than 200 integrated device manufacturers (IDMs), approximately 1,300 fabless companies and more than 125 foundries.

The growth of the semiconductor industry has been fueled by the adoption and proliferation of the PC, the cellular phone and the Internet. Today, these platforms and their offspring have driven an amazing diversification of products and applications, and semiconductors are becoming a larger percentage of all modern electronics.

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Semiconductor intellectual property (SIP) has existed since the advent of the semiconductor industry. In the early years, IC suppliers such as Fairchild, Intel, TI and Motorola developed proprietary SIP (including data and circuit design expertise, process knowledge, packaging test equipment and other items) for their internal use. They fiercely protected their SIP through patents, trade secrets and other legal protections. Occasionally SIP was licensed to third parties, but this tended to be the exception rather than the rule.

Over the last decade, IC design productivity has failed to keep pace with Moore's Law and a “design gap” has emerged. This is despite the development of a $3 billion per year commercial electronic design automation (EDA) industry. In response to this increasing capacity, IC suppliers began looking for ways to close the gap between what engineers could reasonably be expected to design within a given time frame while still meeting schedules, and the capacity of the silicon (the “design productivity gap”). They began developing reusable SIP that contained increasingly complex functionality.

As the foundry model emerged, fabless IC companies adopted a customer-owned tooling (COT) design flow and a block-based design methodology, partly to leverage the cost advantages of the Foundry model, but also to allow mobility of design. Many of them developed their own SIP but outsourced when possible.

SIP is critical for the design and implementation of complex system ICs. As designs become more complex, a greater number of SIP products are being embedded in IC designs. SIP has become a key part of the electronic design process because it can reduce IC development costs, accelerate time-to-market, reduce time-to-volume and increase end-product value; in short, it can provide a solution that enables companies to bridge the “design gap.”

In 1999, over 900 SIP providers existed in the industry; today, approximately 500 SIP companies operate in the semiconductor industry, with roughly 150 or less selling any sizable amounts of IP. The industry is dominated by a few large players.  Consolidation will continue due to the business climate and requirements for high-quality, verified, silicon-hardened IP.

Enter the GSA IP Portal to gain access to the tools, reports, surveys, articles, presentations and white papers that are available regarding the IP industry.

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Before EDA, integrated circuits were designed by hand, and manually laid out. The 1980s mark the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett Packard, Tektronix, and Intel, had pursued EDA internally. In 1981, managers and developers spun out of these companies to concentrate on EDA as a business. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis.

The EDA market is extremely niche oriented. Approximately 70 design niche markets equal more than $1 million dollars. The leading supplier in each EDA product segment averages more than 70% of total market share. In fact, three leading suppliers hold the ten largest revenue producing EDA segments. Revenues in 2008 are expected to be around $5.6 billion, down 11 percent from 2007.

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Smaller, faster, more energy-efficient chips are at the heart of new process development strategies. However, the road to advanced nodes has challenging obstacles along the way. The Wafer Manufacturing Portal provides the latest information, data and resources related to these challenges of this imperative segment of the semiconductor supply chain. Both pure-play foundries and internal wafer fabrication facilities face the following challenges today, among others:

• The increasing capital needed to build and maintain fabs
• Reducing time-to-market
• Providing accurate and complete PDKs
• Coordinating libraries, IP blocks and EDA flows with their respective developers and vendors
• Coordinating test, assembly & packaging technology
• Developing cost-effective process technologies, suitable also for analog & mixed-signal integration
• Ramping-up manufacturing capacity and yield quickly
• Providing high-quality products on schedule
• Continuing legacy node processes

GSA is committed to addressing these and other manufacturing issues, plus driving industry solutions to enable the industry to continue innovating and improving the world.

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The complexities and uncertainties associated with semiconductor (“chip”) manufacturing requires that some level of testing be performed on each chip before being shipped to customers. The extent of testing can range from sample testing for chips deploying straightforward designs and mature manufacturing processes, to several stages of lengthy, fully-functional, multi-temperature testing for chips using the latest technologies.  While many acknowledge that test adds some value to the chip through design debug and verification, yield learning, and the like, test is largely considered a cost of manufacturing.  Thus, chip companies strive to minimize the cost-of-test (COT), which is mainly determined by the test equipment cost and throughput.  As design-for-test (DFT) techniques become more widely deployed, the associated design engineering and silicon area costs are now also components of the COT equation.

Since test equipment must be able to source and capture many channels of the latest high-speed, smart-power, and high-precision signals, the equipment manufacturer business model requires significant investments in research and development, applications engineering, and other support functions.   In addition to maintaining alignment with the latest chip functionality, equipment suppliers continue to drive overall COT reductions through lower channel costs and channel quantities per system – the latter allowing more chips to be tested simultaneously on a given system, thus increasing throughput.  To further manage the overall COT, test equipment will typically be configured to have only the channels and capability needed to test a particular chip, making the manufacturing capacity dedicated to a given chip, or at best, a chip family.  In addition, each chip has a unique list of required tests, making throughput chip-dependent as well.

Fast-paced technology changes and chip-specific test solutions, amplified by the proliferation of system-on-chip (SOC) and system-in-package (SiP) designs, make it difficult for test providers to optimize the utilization of costly test assets and thus maximize their return on investment (ROI) – reducing the economic profits of not only the test provider, but also that of the test specifier and test equipment supplier. This issue is even more of a problem for the test subcontractor, whose founding business model relies on the efficient aggregation of test demand across a diverse set of test specifiers and their chips. The commonly cited one-third of unutilized test capacity across the industry results in a significant economic burden on the entire semiconductor test value chain.

Enter the GSA Test Portal to discover information and collaboration opportunities that will begin to return this lost value back to the semiconductor test industry.

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As a result of the increasing demand to produce more complex ICs, requiring more customized performance specifications, packaging now plays a vital role in facilitating diverse applications through the expansion of available package types.

• There are approximately 1,500 different packages in the marketplace.
• Packaging accounts for approximately 25% of the chip cost.
• IDMs increasing outsourcing adds new competition for packaging services.
• Investments by packaging companies are more controlled to increase profitability and stability—6% to 35% gross profit margin.

The outsourced assembly and test providers market share is almost 45% compared to just 25% in 2003 and 15% in 1995. By 2012, it is expected that at least half of assembly and test services will be outsourced to OSAT companies due mainly to companies choosing to outsource manufacturing and back-end services. Several key growth metrics for the back-end market include:

• SATS market grew 6.6%, reaching $22 billion in revenue (Gartner Dataquest).
• Back-end utilization rates consistently in 80-85% range in 2008 (Gartner Dataquest)
• CAGR for packaging unit shipments = 10% from 2007-2012F (IC Insights)
• Units to grow from 135 billion in 2007 to 217 billion units in 2012F (IC Insights)

*Source: McClean Report, 2008, ITRS 2007 Update

Visit the GSA Packaging portal to get more involved in industry solutions and to view various tools, surveys, articles and reports from GSA to gain further knowledge about the packaging industry.

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Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through microfabrication technology. While the electronics are fabricated using integrated circuit (IC) process sequences (e.g., CMOS, Bipolar, or BICMOS processes), the micromechanical components are fabricated using compatible "micromachining" processes that selectively etch away parts of the silicon wafer or add new structural layers to form the mechanical and electromechanical devices.

MEMS promises to revolutionize nearly every product category by bringing together silicon-based microelectronics with micromachining technology, making possible the realization of complete systems-on-a-chip. MEMS is an enabling technology allowing the development of smart products, augmenting the computational ability of microelectronics with the perception and control capabilities of micro-sensors and micro-actuators and expanding the space of possible designs and applications.

Microelectronic integrated circuits can be thought of as the "brains" of a system and MEMS augments this decision-making capability with "eyes" and "arms" to allow micro-systems to sense and control the environment. Sensors gather information from the environment through measuring mechanical, thermal, biological, chemical, optical and magnetic phenomena. The electronics then process the information derived from the sensors and through some decision-making capability direct the actuators to respond by moving, positioning, regulating, pumping and filtering, thereby controlling the environment for some desired outcome or purpose. Because MEMS devices are manufactured using batch fabrication techniques similar to those used for integrated circuits, unprecedented levels of functionality, reliability and sophistication can be placed on a small silicon chip at a relatively low cost.

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Analog/Mixed-Signal (AMS) and radio frequency (RF) technologies which serve the rapidly growing wireless communication market represent essential technologies in the semiconductor space. AMS/RF circuits convert input radio signals into digital data which can be passed to a baseband processor for data processing. This type of conversion enables the functionality of cell phones and other wireless devices.

Paul Double, Director, EDA-Solutions, chairs the Analog/MS Interest Group in Europe, whose formation was encouraged by the EMEA Advisory Council Europe, Middle East and Africa (EMEA) Leadership Council.  On the other side of the pond in North America, Sanjay Krishnan, Business Manager, Maxim Integrated Products, will chair an Analog/MS group in North America. The two groups will work cooperatively as one Interest Group. For more information on how to join, contact Lisa Tafoya at ltafoya@gsaglobal.org or at 972.866.7579 ext. 116. 

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