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Morning Keynote Presentation
"The Future of the Foundry: Semiconductor Manufacturing in the 21st Century"
Ajit Manocha, Executive Vice President and Chief Manufacturing Officer, Philips Semiconductors
While semiconductors continue to proliferate as a natural element of applications used in daily life, the technical challenges and the economic dynamics of semiconductor manufacturing are anything but natural. The many challenges that fabless companies face, including new transistor concepts, right-first-time design and designing for manufacturing have forced the industry to look for technical solutions and business models that are far from obvious.
In his keynote presentation, Ajit Manocha will present Philips’ views on what the future holds for semiconductor manufacturing, comparing the economics of semiconductor manufacturing with the economic consolidation of manned space missions. Another main focus of the keynote will be how the growing interdependence between IDMs, fabless semiconductor companies, foundries and assembly subcontractors is addressing the demands of emerging electronics applications and how to make the most of this change.
Distinguished Speaker Keynote Presentation
"Building Lasting Supply Chain Relationships"
David D. French, President and Chief Executive Officer, Cirrus Logic, Inc.
During his presentation French will elaborate on the following key points:
- Developing a successful model for total outsourcing
- Joint collaboration for long-term, mutual success
- Challenges of inventory management
Advantest America, Inc.
“The Value of an OPENSTAR® Ecosystem on the Second Generation Outsourcing Model”
Sergio Perez, Vice President, Business Development
The fabless semiconductor community is primed to enter the next phase of its business model. This second generation outsourcing model must now more effectively address the challenges of a distributed business environment and the impact of a global industry driven by cost sensitive consumers. The key objective for the second generation framework is higher efficiency, seamless integration and cost effectiveness.
In 2004, the Semiconductor Test Consortium launched the Open Architecture program and the OPENSTAR ATE architecture to facilitate the deployment of a powerful ecosystem in support of the second generation outsourcing model.
This presentation will provide an update on the key elements of the Open Architecture ATE program and the power of the OPENSTAR Ecosystem to enable the next generation of the outsourcing business model.
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Apache Design Solutions
"Silicon Signoff Challenges for 45nm SoC"
Andrew Yang, CEO
Power and noise are key contributors to signoff challenges of 45nm designs. Factors such as dynamic power, leakage current, temperature variation, substrate and package noise, all impact the integrity of SoCs and must be analyzed and managed to ensure silicon signoff success. This presentation will discuss Apache's product offerings, which address these key challenges associated with power and noise. Apache's solution improves design productivity and quality of results.
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Chartered Semiconductor Manufacturing
"We Collaborate. You Win: How the Common Platform Collaboration is Changing the Industry at the Leading Edge"
Dr. John Martin, Vice President of Strategic Alliances and Partnerships and Walter Ng, Senior Director of Platform Alliances
Facing increasing technology complexity, soaring design costs, new DFM/DFY challenges and aggressive market windows, designers are taking a hard look at their business models and looking for new, innovative models and solutions. How can you reduce costs and reduce risk, while grappling with complex design and manufacturing challenges and still hit aggressive market windows? The answer for most companies is -- you can’t by extrapolating existing methods -- if you go it alone. Optimizing performance, cost and time to market in the Nano Age demands an integrated, collaborative approach across the value chain and access to the new, innovative techniques. So how can you access technology innovation and benefit from the early adopters' experiences, while not surrending control over your design and still maintaining flexibility?
Chartered has been a pioneer in industry collaboration and providing access, most recently as part of a technology joint-development agreement with IBM, Infineon and Samsung, that’s led to the breakthrough Common Platform approach that enables companies through access to technology innovation and multi-source flexibility. The Common Platform is also pioneering a new open and shared economic model in the industry with innovative DFM solutions and methodologies, based on open third-party EDA/DFM tools.
The collaboration is credited with being the new model on which semiconductor manufacturing should be based in order to deal with today’s challenges. This presentation will discuss how you can benefit from this collaborative model, mitigating risk, maintaining flexibility and enjoying continued opportunity for differentiation.
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Entrepix, Inc.
“Improving Fab Performance through CMP Outsourcing"
Tim Tobin, President and CEO
The growing demand for Chemical Mechanical Polishing (CMP) is the direct result of Moore’s Law with more devices being manufactured at advanced technology nodes, and this is driving both end users and material suppliers to seek alternatives to support their CMP requirements. Many IDMs and consumables suppliers are now using CMP outsourcing to address both their development and production requirements. In response, Entrepix is introducing CMP FastForward™ as a complete suite of CMP outsourcing solutions that support process characterization and development through support of initial ramp and full production outsourcing. Entrepix’ CMP FastForward™ brings significant cost reductions and accelerated time to-money by eliminating traditional capital investment and the associated lead time required to implement internal CMP capabilities.
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Fujitsu Microelectronics America, Inc.
“Resolving the Challenges of Deep Submicron Process Technology"
Paul Little, Manager, Methodology Development
Performance increases, reduced power consumption and smaller die sizes are some of the driving forces behind the move to 65nm. However, the experiences seen at the 130nm and 90nm nodes have left many discussing the challenges involved in moving to the leading edge. DFM, timing, power and signal-integrity closure are all factors in successful implementation of the 65nm technology. To help fabless customers and partners migrate successfully to its 65nm node, Fujitsu enhances the traditional foundry model with an array of optional design and methodology services. With a long history as an IDM, Fujitsu has built a wealth of knowledge in the complete product development cycle. As such Fujitsu provides support in many specialties not available at traditional foundries.
Combining advanced process control with continuous feedback from its manufacturing and reliability groups, Fujitsu has built a tremendous DFM knowledge base, which can be used to minimize the risks in the manufacturing process. With leading-edge, third-party EDA tools combined with in-house CAD development, Fujitsu enhances the design flow with services such as full board/package/die simulation for power integrity and statistical STA. Fujitsu's optional foundry services cut the total cost for design and verification, improve time-to-market and provide access to world-class 65nm technology for U.S. fabless customers.
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IBM
"Overview of IBM Foundry Offerings"
Dr. Teddy O'Connell, Client Manager, Wireless Sector - OEM Microelectronics
This presentation will give an overview of IBM's RF/Mixed Signal and Image Sensor technologies. Details will be provided regarding IBM's process technologies and Foundry Enablement along with the business support model from IBM and it's partners.
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Impinj, Inc.
"Concerns and Cautions When Incorporating NVM into an SoC"
Larry Morrell, Vice President, IP Products
Many IC design projects are now calling for nonvolatile memory. Choices include: FLASH, OTP, EE, Fuses and Logic NVM. Each technology solution is well-suited to particular application problems and each one has its own strengths and weaknesses. This presentation will discuss the design sweet spots for each NVM technology and outline both the design and manufacturing considerations when incorporating NVM. Tradeoffs of wafer cost, silicon area, data security, testing costs, reliability and programming usage models provide a complex tapestry of optimized choices for the user. Learn about these choices and how to evaluate solutions offered by foundries and IP suppliers.
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IPextreme, Inc.
"IP is Dead, Long Live IP – Structural Changes in the Semiconductor Industry"
Trent Poltronetti, VP Marketing
There are fewer pure semiconductor IP companies today than just a few years ago. Is this proof the IP industry is dying? This presentation will examine long term semiconductor trends and their implications that show why IP usage and revenue will continue to grow strongly and moreover why traditional chip manufactures must embrace an IP strategy for long term survival. These structural changes are also creating new needs in the semiconductor industry which is driving the growth of new forms of IP companies.
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Jazz Semiconductor
"High Speed, High Performance, High Voltage - The Next Generation of Foundry"
Dr. Marco Racanelli, Vice President of Technology and Engineering
Modular foundry technology with high speed, high performance, and high voltage analog features is enabling the realization of innovative and highly integrated analog products in wireless, power management, and high speed analog markets. Within a 0.18µm technology node today, features such as SiGe devices reaching speeds of over 200GHz, RF LDMOS devices for power amplifier integration, high voltage devices that can operate at 40V with very low on-resistance, and high quality MIM capacitors with densities as high as 5.6fF/µm2 are available as modules that can be added to a common CMOS platform enabling the integration of RF, precision analog, digital, and power management functions on a single die while allowing easy re-use of both digital and analog IP across products of varying complexity. In this presentation, we will describe these features as implemented in modular platforms from 0.5µm to 0.13µm nodes as well as discuss the outlook for future technologies that stretch the boundaries of silicon into areas today occupied by III-V materials and integrate new devices such as MEMs enabling even higher levels of analog integration.
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LogicVision, Inc.
"Innovations in Yield Learning"
Steve Pateras, Senior Director of Strategic Technology
The DFM space is still rapidly evolving and although not everyone agrees on what solutions and technologies makes the most sense, most agree on the ultimate goal: improving yields. LogicVision offers a complementary and pragmatic approach to this problem. An often overlooked fact about BIST is that it is not only great at finding defects for go-nogo testing, but it also provides a great way of extracting detailed failure and performance information throughout the die. Hidden within this data are pointers to factors limiting the design’s yield. LogicVision’s unique automated data mining and analysis capabilities are capable of automatically uncovering these yield-limiting factors. Depending on the nature of the problem, the reported information is then used directly by designers to modify the design, or by the fab to adjust the process, or both. This post silicon process is called Yield Learning and has been identified within the recently published ITRS roadmap as the highest priority item for dealing with decreasing yields.
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LTX Corporation
"X-Series Fusion: Built for the Way Fabless Companies Test"
Steve Wigley, Vice President of Product Marketing
This presentation will discuss the application of LTX's X-Series Fusion Test Systems to address the challenges and opportunities faced by fabless companies. It will cover the overall performance, flexibility and scalability of the X-Series, including the recently introduced configurations, and the advantages the series provides.
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Magma Design Automation
"Talus – The Path to Profitable 65nm IC Design"
Kam Kittrell, General Manager, Design Implementation Business Unit
At the 65-nm node, addressing IC complexity requires larger design teams and longer development cycles, driving costs to $30 million for a single chip. In response to customers’ need to reduce costs and accelerate the design flow, Magma is once again changing the world of chip design. With the release of the Talus IC implementation product line, Magma cuts IC design cost by delivering true electronic design automation.
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MagnaChip Semiconductor, Inc.
"Specialty Foundry for the Next Wave: Mixed Signal and High Voltage Fusion"
Andy Brown, Vice President, Sales
MagnaChip is a leading specialty foundry focused on delivery of unique, advanced process technologies. In the presentation, MagnaChip will describe how it is positioning its technology roadmap and services to enable customers to meet the requirements of emerging applications that require the fusion of mixed signal and high voltage.
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Mentor Graphics
“Implementing a DFM Methodology: Safeguarding the Fabless Model”
Tony Nicoli, Director of Marketing, Design-to-Silicon Division
With each new process node, additional defect mechanisms appear and hinder the ability to achieve desired yield. The trend toward declining yields has created resurgence in the application of design for manufacturing (DFM) methodologies. Design for manufacturing in nanometer technologies has the potential to change almost every aspect of the IC design and manufacturing process. It has radically changed the lithographic process in manufacturing, and continues to mold advancements in IC manufacturing equipment and materials. For the design team, it beckons an extensive review of current design practices. Will concurrent change in both the design and manufacturing disciplines overcome the challenges we face? Will new technologies continue to provide the safeguards required in the fabless model to protect everyone’s IP?
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MOSAID Virtual Silicon
"MOSAID Mobilize(TM) Ultra-Low-Power Memory Compiler"
Craig Thrower, Director, Mobilize Engineering
The Mobilize Single-Port SRAM Compiler generates a high density, high performance, very low leakage memory instance for embedded IC applications. The Mobilize SRAM Compiler provides reduced die area with efficient design and use of the TSMC UHD bit-cell. The Virtual Silicon Gate Bias and virtual ground technology dramatically reduces leakage in both Sleep Mode with data retention and Deep Sleep Mode without data retention. The generated instances provide both low power and high performance suitable for consumer electronics and high performance computing in standard TSMC 90nm G and LP processes.
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Right90, Inc.
"Hidden Margin: Exposing Opportunities in Planning and Execution"
Kim Orumchian, CEO
Do you know whether your ops group is better at forecasting that your sales group? Do you find that there is no such thing as a consensus forecast in your company? Do you make resourcing decisions according to forecast revenue only to get surprised by margin results when the numbers roll up?
If so, hear how Right90 has helped customers raise their enterprise gross margin and reduce overbuild by providing a hosted software profitability management service. Right90 shows which internal forecasters to trust, exposes where margin and profitability will be coming from at a granular level, and creates a dynamic roadmap to let companies act on the issues that lie between plan targets and a successful outcome for the quarter.
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SAP Labs
"Integrating the Enterprise...Bringing the Power of Real-Time Information to Fabless Semiconductor Manufacturers"
Kevin Flynn, Solution Manager and Jeff Nestel-Patt, Director of Marketing, Brooks Software
The accelerating trend of distributed manufacturing is driving the need for greater visibility to real-time information throughout the enterprise. Success in the demand-driven world requires using this information for more informed business decision-making. How can fabless semiconductor manufacturers benefit as interoperability is extended throughout their supply chains?
SAP and Brooks give fabless and fab-lite manufacturers the solutions they need to thrive in an increasingly complex world. Connecting SAP’s business systems with Brooks Software’s plant floor systems improves enterprise performance by increasing capacity and asset utilization, and providing real-time visibility to work-in-process inventory from the shop floor through packaging to improve on time delivery to commit.
Building on SAP’s evolving Enterprise Services Architecture (ESA) and leveraging the Powered by Netweaver® platform, Brooks and SAP are developing solutions that offer powerful analytics and business intelligence to improve manufacturing efficiency. Learn how you can benefit when the world’s leading provider of business systems works with the world’s leading supplier of manufacturing execution systems.
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Semiconductor Insights
"Best Design Practices to Maximize Layout, Gate Density, and Power Management in Applications Processors"
Peter Di Paolo, Technology Manager, Communications
Semiconductor Insights will present findings from recent analyses showing the design elements used to achieve best design practices for maximizing layout, gate density, and power management in applications processors. The innovations will be demonstrated through analyzing standard cell blocks. To highlight best design practices, SI will excerpt content from our report on Texas Instruments' OMAP2420, a multicore applications processor geared towards high-end handsets. SI will explore some of the elements used in TI's SmartReflex Power Management techniques within the standard cell core.
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Siliconaire, Inc.
"A New User-Friendly Outsourcing Model for Fabless Semiconductor Companies"
Ron Das, President and CEO
This presentation describes a new model whereby a team of operations professionals, with proven track records in building fabless semiconductor start-ups, provides the interface between systems innovators and semiconductor suppliers on an as-needed basis to maximize efficiency, minimize risk and enable higher gross margins for the start-up.
Such a model works to insure successful implementation of digital, mixed-signal and RF of SOC’s and SIP’s by: utilizing a proven methodology, offering best-of-class talent, helping start ups become self-sufficient at their own pace as they grow, minimizing mistakes to facilitate first time success, preserving the start-up’s limited funds to concentrate on its own core-competency, reducing COGS through effective negotiations with suppliers and enabling fabless semiconductor companies to enjoy full gross margins from direct vendor relations. With such a model, a fabless start-up can immediately enjoy the benefits of access to a world-class team, and at the same time build close relationships with best-of-class suppliers.
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Simucad Design Automation
"Simucad PDK-Based AMS/RF Design Flow"
Ken Brock, Vice President of Marketing
Analog, mixed-signal, and RF integrated circuit designers need a full set of custom IC design tools with complete process design kits (PDKs). This presentation shows how Simucad integrates its best-in-class, multi-core optimized software products with experienced support and PDK development services to provide a complete PDK-based design flow. This flow includes interfaces with leading third-party design tools and is available on Linux, Solaris and Windows. Simucad is a spin-off of Silvaco International.
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STATS ChipPAC
"RF Module Assembly and Technology Integration"
Eric Gongora, Director of SiP/CSMP Technology and Dr. Robert Frye, Consulting Director of Technology
This presentation will examine current RF Module Assembly technologies, materials and processes (Wirebond, Flip Chip, Integrated Passive Device), technologies that are in development over the next 1-2 years and concepts that are being discussed for the next 3-5 years.
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Synopsys
"A Practical Approach to Measuring and Improving Design Productivity using Synopsys® Pilot Design Environment and DesignWare IP"
Ravi Srinivasan, Sr. Product Manager, Professional Services
Navraj Nandra, Director Product Marketing, DesignWare IP
This presentation will outline a practical methodology to identify, establish, capture and improve design productivity. Leading customers have deployed Synopsys® Pilot Design Environment and Synopsys® DesignWare IP to help measure and improve design productivity. Synopsys® Pilot Design Environment is an open, ready-to-use design system. Pilot includes a modular Synopsys RTL-to-GDSII design flow plus methodologies and utilities to tackle the most common CAD and project challenges. Synopsys® DesignWare IP is the most widely used, silicon-proven IP. DesignWare contains a growing portfolio of on- and off-chip connectivity IP with a complete PCI Express IP and USB IP solutions. Come see how leading fabless companies have leveraged these Synopsys solutions to improve their design team productivity.
How will it specifically benefit fabless companies? Configure Pilot with the existing tools & infrastructure to improve tape-out predictability with multi-site and multi-project development. Adopt silicon-proven, compliant, high-speed interconnect IP to minimize project risk.
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Tensoft, Inc.
"IPO Readiness and Sarbanes-Oxley Compliance for Fabless Finance and Operations"
Bob Scarborough, CEO
In today’s competitive business environment, fabless semiconductor organizations need to continually create and sustain shareholder value. Attend this presentation to learn how fabless start-ups can methodically build a foundation for IPO readiness early on, and how public fabless companies can avoid some Sarbanes-Oxley pitfalls that are unique to this industry.
Sarbanes-Oxley compliance efforts directly impact a number of the key factors that affect IPO readiness. This presentation discusses how, when and where in a fabless company’s growth cycle business systems and processes can be added to support both Sarbanes-Oxley compliance and IPO readiness as the company grows. It also outlines the industry-specific requirements and unique business system needs of fabless semiconductor companies. The session concludes with a proposal for using Sarbanes-Oxley compliance concepts to help improve and streamline fabless business processes.
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Teradyne, Inc.
"Test Solutions for Emerging Integrated Technologies"
Dan Hamling, Business Manager, Fabless/Subcon
As consumers continue to drive an increasingly larger percentage of overall semiconductor demand, the rate at which new levels of functionality and reductions in cost are brought to market will also increase. This trend is unmistakedly evident in the intensely fast pace of the fabless segment of the industry. Semiconductor Automatic Test Equipment (ATE) suppliers are thus challenged to provide solutions that both cover a broad range of integrated technologies as well as deliver highly efficient multi-site test economics.
Teradyne's FLEXTM Platform of products is based on an architecture that is aligned to these two key dimensions of technology and economics. Unlike alternatives, the FLEX Architecture was designed from the ground up to virtually eliminate tester overhead, achieving near-perfect parallel test efficiency - not just for digital devices but also for those having power management, memory, analog, RF, and other integrated technologies. Integral components of the FLEX Architecture also include its IG-XL Pure ParallelTM software, enabling rapid multi-site program implementation, and its OpenFLEXTM instrument design standard, enabling rapid platform technology coverage expansion.
This presentation will review these key features of the FLEX Architecture, and describe how they address the technology and economic demands in the fabless arena. The presentation will further examine two emerging technology case studies, specifically revealing the FLEX Platform solution to the challenges of high-speed serial and stacked memory integration.
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Tower Semiconductor
"Advanced Foundry Solutions: Specialized Technologies, Customization and Support"
Rafi Nave, CTO
As the Semiconductor industry matures and the foundry sector establishes itself as a primary category, one observes in that sector some key sub-categories. The most prevalent is the distinction between the large foundries, such as TSMC, UMC, Chartered and SMIC, and the smaller foundries that consist, each, of one or a small number of FABs. It is apparent that the smaller foundries cannot compete heads-on with the larger foundries on their own turf. Namely, they cannot keep up with the technology race of providing ever smaller geometries, with very costly equipment investment and process development, nor can they secure the huge capacity requirements expected by the large Fabless customers.
Hence, the smaller foundries need to provide differentiation in some form. The two most common approaches are: Specialized Technologies and Customizations. The former implies becoming an expert in niche markets that require unique technologies. The latter implies application of engineering expertise to develop special process, device or design solutions that are required exclusively by a specific customer. An additional element that may provide differentiation is the level and quality of the support that customers may receive from the smaller foundries and the intimate relations that may evolve as a result.
This presentation will dwell on these aspects with examples, primarily from Tower Semiconductor's specialized offering and vast experience, showing how these are utilized to help its customers improve technical and marketing positions in the highly competitive marketplace.
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