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Tuesday, January 23, 2007
| 8:00
AM - 9:00 AM |
Registration |
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| 9:00 AM - 11:30
AM |
SiP Tutorials
The four SiP tutorials
are designed to provide a foundation
for all attendees to participate
fully in the conference. One tutorial
track focuses on SiP technology
and addresses the drivers, applications
and issues in SiP solutions as
well as emerging 3D integration
at the wafer level. The other
tutorial track focuses on tools
and applications and addresses
SiP co-design flow and simulation
and the important considerations
of Design for Test (DFT) in the
SiP environment. |
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| 9:00 AM - 10:00
AM |
Track A-1
SiP Technology
Focused Tutorials
SiP Driver Applications and
Issues
Jan Vardaman, TechSearch International,
Inc. |
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Track B-1
Tools and Application
Focused Tutorials
Co-Design Flow/Modeling &
Simulation for SiP
Robert Mullen, Cadence Design Systems,
Inc.
Dr. Amit Agrawal, Broadcom Corporation |
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| 10:00 AM - 10:30
AM |
Morning Break |
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Morning Break |
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| 10:30 AM - 11:30
AM |
Track A-2
3D Integration at Wafer Level
TSV Technology
Dr. Sitaram Arkalgud, Sematech
Corporation
Dr. Susan Vikavage, Sematech Corporation |
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Track B-2
DFT for the SiP Environment
Alfred Crouch, Inovys Corporation |
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| 11:30 AM - 12:30
PM |
Networking Luncheon |
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| 12:30 PM - 12:45
PM |
Conference Official
Opening Address
Chris Malachowsky, Co-Founder, NVIDIA Fellow and Senior Vice President of Engineering and Operation,
NVIDIA Corporation |
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| 12:45 PM - 1:15
PM |
Keynote:
"SiP Application
and Business Trends"
Jim Walker, Gartner Dataquest |
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| 1:15 PM - 2:00
PM |
Keynote:
"SiP Technology Overview"
Dr. Homing Tong, ASE Group |
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| 2:00 PM - 2:30
PM |
Afternoon Networking
Break |
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| 2:30 PM - 4:45
PM |
Case Studies:
Advanced SiP Applications - Methodologies
& Lessons Learned
Different market segments
and applications have different
needs and drivers. In this session,
we have invited a cross-section
of industry experts to present
their methodologies and the lessons
they have learned from leading
edge applications in diverse market
segments. |
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| 2:30 PM - 3:15
PM |
RF/Mixed Signals
Tom Gregorich, QUALCOMM |
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| 3:15 PM - 4:00
PM |
High Performance Applications
Dr. Jie Xue, Cisco
Systems |
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| 4:00 PM - 4:45
PM |
Consumer System Integration
John Savic, Motorola |
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| 5:00 PM -7:00
PM |
Networking Cocktail
Reception |
Wednesday, January 24, 2007
| 8:00
AM - 9:00 AM |
Registration & Breakfast
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| 9:00 AM - 9:30
AM |
Keynote: "SiP
& Systems Integration - Perspective
from ITRS"
Dr. W.R. (Bill) Bottoms, NanoNexus &
3MTS |
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The diverse market drivers led
by the fast-changing consumer
segment have ignited a surging
renaissance in innovations in
SiP design and system integration.
The speaker will articulate the
perspective from ITRS, particularly
from the ITRS Assembly & Packaging
International Technical Working
Group. |
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| 9:30 AM - 10:00
AM |
Keynote: "SiP Approach in Samsung"
Dr. Jason Cho, Samsung |
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How are SiP technologies utilized
in this well known and well respected
consumer electronics and device
manufacturer? |
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| 10:00 AM - 10:30
AM |
Morning Break |
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| 10:30 AM - 12:00
PM |
Panel Discussion:
"SiP Co-Design Flow Challenges "
Panelists:
- Flynn Carson, STATS ChipPAC
- Kim Chen, TSMC
- David Cheskis, Jazz Semiconductor
- Matt Kaufmann, Broadcom Corporation
- Jochen Reisinger, Infineon
Technologies
- Hem Takiar, SanDisk Corporation
What are the user perspectives
of SiP co-design tools?
Industry user experts from
representative stake holders
in the SiP food chain will articulate
the visions for future co-design,
simulation and test environments. |
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| 12:00 PM - 1:00
PM |
Networking Luncheon |
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| 1:00 PM - 2:30
PM |
Panel
Discussion: "Co-Design/Simulation
Tool Vision/Roadmap, To Align Tool Supply Chain Development with The SiP Design Requirements"
Panelists:
- Michael Breneman , Ansoft
Corporation
- Keith A. Felton, Cadence
Design Systems, Inc.
- Humair Mandavia , Zuken
Inc.
- An-Yu Kuo, Optimal Corporation
- Kevin Rinebold, Sigrity,
Inc.
- Per Viklund, Mentor Graphics Corporation
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| 2:30 PM - 3:00
PM |
Afternoon Break |
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| 3:00 PM - 4:30
PM |
Panel
Discussion: "SiP Test Methodology, the Need for DFT, Debug Capability and Improving SiP Yields"
Panelists:
- Bruce Cory, NVIDIA Corporation
- Alfred Crouch, Inovys Corporation
- Merrill Hunt, QUALCOMM
- Ajay Khoche, Verigy
- James McEleney, Teradyne
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| 4:30 PM - 5:00
PM |
Wrap Up: "SiP
in the Fabless Environment"
Dr. Bill Chen, ASE Group |
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