Suppliers Forum & Networking SeriesApril 17, 2007

AGENDA

Tuesday, April 17, 2007

 

Time Track 1
Fabless Supply Chain Management Software
Track 2
Assembly and Test Services
11:30 a.m. - 1:00 p.m. Registration
1:00 p.m. - 1:50 p.m. Oracle STATS ChipPAC
1:50 p.m. - 2:40 p.m. Camstar  
2:40 p.m. - 3:30 p.m. Serus LogicVision
3:30 p.m. - 4:20 p.m. Tensoft  
4:20 p.m. - 5:10 p.m. Scalar Soft Teradyne
5:15 p.m. Networking Cocktail Reception

 

 

Track 1
Speaker information and synopsis

Oracle
Presenter: Coming Soon
Presentation Title: Coming Soon
Synopsis: Coming Soon

Camstar
Presenter: Steve Rolston, Senior Product Manager, Semiconductor Manufacturing
Presentation Title: Full Visibility, Traceability and Yield Management with Global Subcontractors
Synopsis: In this presentation, you will learn how a fabless semiconductor company is using Camstar InSite to manage their global suppliers.
From wafer orders and instructions to lot transaction status and history reports, you will discover how this company is orchestrating the entire
supply chain as a maestro conducts his symphony in a seamless way.

Serus
Presenter: Coming Soon
Presentation Title: Coming Soon
Synopsis: Coming Soon

Tensoft
Presenter: Coming Soon
Presentation Title: Coming Soon
Synopsis: Coming Soon

Scalar Soft
Presenter: Coming Soon
Presentation Title: Coming Soon
Synopsis: Coming Soon

Track 2
Speaker Information and Synopsis

LogicVision
Presenter
:Steve Pateras, Senior Director Strategic Technology
Presentation Title
: Taming the 65nm Embedded Memory Test & Yield Problem
Synopsis
: Reduced manufacturing costs through:

  • Test time optimization through run-time selection of most appropriate test algorithm
  • Single insertion memory repair on any tester
  • Multi-site test and repair on any tester
  • Full control of quality/test time trade-offs. Provides insurance for unanticipated defects issues
  • Major test time reduction when dealing with repairable memories, as defect data need not be extracted from the chip
  • Major test time reduction when dealing with memories with both spare rows and spare columns to achieve manimum yield levels

STATS ChipPAC
Presenter: Dr. Raj Pendse, Director of Advanced Packaging
Presentation Title: Coming Soon
Synopsis: Discuss cost effective flip chip and wafer level packaging solutions for applications requiring a smaller form factor, higher I/O and enhanced thermal and electrical performance.

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