| Time |
Agenda Item |
| 9:00 a.m. – 9:30 a.m. |
Session Introduction – The IP Ecosystem Today
Session Moderator: Raminderpal Singh, Senior Technical Staff Member, IBM and IPecosystem Technical Lead, GSA
GSA has heard in many forms and from companies throughout the supply chain that relationships between IP vendors, IP integrators, EDA and Foundries are sometimes complex /difficult and even frustrating.
- What problems are faced today in IP evaluation?
- Where are the hidden costs to buying new IP or designing in new technologies?
- What is needed?
9:30 a.m. - 9:40 a.m. - Opportunity to place Tool on Tutorial attendees laptops |
| 9:30 a.m. – 10:00 a.m. |
Case Studies using two common types of IP with the GSA Hard IP Quality Risk Assessment Tool. This session will walk through two types of IP, providing insights on how to use the tool, questions to answer, demonstrate what the tool answers, what the data shows and how to make decisions on quality and licensing risks.
Presenter: David Schwan, Engineering Manager, CAD and Layout, RF Micro Devices (RFMD)
Within this portion the following IP examples will be discussed:
- 128bit OTP block
- 10Bit 200Mhz A/D converter
|
| 10:00 a.m. – 10:30 a.m. |
Discussion on how these risk assessment tools are used in a collaborative environment
Presenter: Walter Ng, Vice President of Enablement Alliances, Design Services Division, Chartered Semiconductor Manufacturing Inc.
In this presentation, we will discuss the changing landscape of the Foundry industry and the implications for the IP business.
We will then discuss how the GSA Hard IP Quality Risk Assessment Tool supports collaboration by providing a tool to evaluate IP, which may be developed via different channels and in conjunction with different partners.
The discussion will demonstrate how the GSA Hard IP Quality Risk Assessment Tool provides a level of standardization, which is being used by companies throughout the industry to benefit end customers by objectively communicating IP information to make key decisions.
Tutorial participants will have a first-hand example of how different partners use different language around IP and how they specify and qualify IP based on legacy approaches. Participants will learn how IP vendors, Chip Manufacturers and their customers can align and streamline the process using such tools. This establishes a common language throughout the supply chain to the customer. |
| 10:30 a.m. – 11:00 a.m. |
Emerging trends in IP and how the ecosystem is working to aggregate and disseminate data to add value to chip integrators.
Presenter: Adam Traidman, President and CEO, Chip Estimate Corporation
- Getting IP quality data to the chip design community.
- Searching, exploring, comparing IP by quality and other parameters
- Leveraging this data to make better chip planning decisions
- 30,000 foot view of IP usage across the industry
- Trends observed in over 50,000 chip estimations in the last 18 months and what the future holds.
|
| 11:00 a.m. - 12:00 p.m. |
Open Forum Discussion on Technology and Manufacturing Tools Needed Within the Industry
Session Moderator: Raminderpal Singh, Senior Technical Staff Member, IBM and IPecosystem Technical Lead, GSA
IPecosystem Technology & Manufacturability Initiatives -- The presenters will hold a structured discussion with the attendees (potentially breaking up into smaller teams) on the pain points and root causes behind hidden costs when chip integrators and IP vendors decide on technologies and foundries. Important themes include ability to compare technology and library offerings of foundries in an even manner, and ability to assess manufacturing risks at foundries.
The final portion of the tutorial will provide discussion that GSA’s IP Interest Group and Working Groups will utilize to develop the third and fourth tools to be introduced to the industry later this year. |
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