Program Abstracts
"High Performance System-in-Package (SiP) for Networking Products"
Mark V Brillhart, VP, Technology and Quality / Customer Value Chain Management, Cisco
Increasing demand for bandwidth and data rate in high performance internetswitching and routing systems has resulted in the use of higher Si integration of functionalities (such as high speed Serdes, embedded SRAM, DRAM, and TCAM) over multiple product generations. However, the demand for bandwidth and date rate has out-paced the increase in Si gate density which results in requiring both larger die size and a higher number of I/O for memory interfaces. This demand drives the need for continuously evolving advanced packaging technologies. System in Packaging (with ASIC and memories) offers the benefits of reducing total I/O used in board level interconnect, improves noise margin at the system level, and increases functionality between Si technologies nodes by simply scaling interconnect. This presentation will cover the technical and reliability challenges along with radical changes in collaboration among all members of a multi-tier supply chain.
“Value-driven Memory Technology for the Future Semiconductor Market”
Dr. Oh-Hyun Kwon, President of the Semiconductor Business, Samsung Electronics Co., Ltd.
As the seamless communication and computing continues to evlove, customer demand for improved set performance is on the rise. Memory chip makers need to collaborate closely with logic companies in order to create new value to customers and facilitate the convergence of cloud computing and seamless connectivity.
"Eliminating DRAM Performance Bottlenecks in Embedded SoCs"
Dr. Drew E Wingard, Co-founder and Chief Technology Officer, Sonics, Inc.
Today’s fully-functional embedded SoCs, such as those featured in video products, require enormous amounts of memory. Limited available bandwidth at the DRAM memory continues to be one of the most significant challenges in the design of these SoCs. Many SoCs have 50, 100 or even more cores, each demanding carefully tuned access to higher bandwidth DRAMs. Burst sizes in DDR3 systems have doubled, introducing an efficiency penalty that can dramatically compromise system performance. Increasingly, SoC designers are looking for innovative memory technologies to better maintain and even optimize on-chip performance while increasing memory bandwidth— without additional costs or system degradation. The presenter will detail the latest memory innovations to eliminate DRAM performance bottlenecks in SoCs, and offer a cost-sensitive approach for increasing memory bandwidth in SoCs found in the world’s most popular home entertainment and mobile devices.
"High Performance Embedded Memory and Memory Hierarchy in High End Systems"
Subramanian S. Iyer, IBM Systems and Technology Group
Memory has always played a central role in high end systems. At the very high end it can contribute to more than a third of the system cost. Similarly, it can contribute up to a third or more of the power consumption of the system. Both these parameters need to be optimized through a judicious choice of the memory hierarchy and the introduction of new memory technologies in the hierarchy.
The current talk will focus on two trends: the development of new embedded memory technologies such as embedded DRAM and 3D integration and the role they are playing in high end systems and the impact that new non-volatile memories, including Phase Change and one-time-programmable ROMs can play in optimization of the memory hierarchy.
Finally, we will address the constructive role that collaboration can and will play in development of a differentiated optimized memory hierarchy.
"Abstract: Forging a Future in Memory — New Technologies, New Markets, New Applications"
Ed Doller, Chief Technology Officer and Corporate Vice President, Numonyx
The current non-volatile memory trends are allowing new applications such as solid-state drives (SSD) in enterprise systems to become a reality. However, scaling challenges associated with charge storage based memory (e.g., NAND) will undoubtedly add cost and/or performance hurdles that may ultimately limit SSD market penetration. Additionally, as customers begin to re-architect their systems to take full advantage of an SSD, they are left wanting for even more performance. Responsiveness in many of these initial use models is directly dependent on random latency, ranging from the time to access code or meta data, to the time it takes for critical information to be committed into a durable, reliable state. Phase change memory (PCM), while in its infancy, has the ability to scale well beyond charge based storage devices and provide non-volatile DRAM like latency closing the gap between storage and main memory.
"Future RAM emerging memory technologies and their applications"
Pierre Fazan, Founder, Chairman & Chief Technology Officer, Innovative Silicon, Inc.
Scaling 6T SRAM and 1T/1C DRAM bit cells below the 50 nm node dimension represents a serious challenge. Variability and leakage issues seriously affect memory functionality; contacts, devices aspect ratios and capacitor materials approach manufacturing limits. Recently, new concepts have been proposed to address these scaling and performance limitations. Among them, the floating body or capacitor-less RAM cell is one of the leading contenders as it is simple, uses only conventional materials and is therefore fully compatible with CMOS processes. Following the introduction of a technology exploiting a BJT operation, capacitor-less RAM cells are now well suited to replace embedded and standalone SRAM and DRAM cells in sub 50 nm embedded and standalone memory applications.
