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Featured Speakers

Joel Hartmann

Joël Hartmann
STMicroelectronics

Dr. Chenming Hu

Dr. Chenming Hu
University of California, Berkeley

Subramanian Iyer

Subramanian S. Iyer
IBM

Subramani Kengeri

Subramani Kengeri
GLOBALFOUNDRIES

Nick Yu

Nick Yu
Qualcomm

Speakers

Raman Achutharaman Shung Chieh Dr. Subramanian S. Iyer Steve Pateras
Jim Aralis Matt Crowley Subramani Kengeri Pushkar Ranade
Mr. Paul Boudre Mr Joël Hartmann Liam Madden Rich Rice
Mark Brillhart Prof. Chenming Hu David McCann Mr. Nick Yu
Dr. Roawen Chen

Raman Achutharaman

Raman Achutharaman Corporate Vice President, Strategy & Marketing, Silicon Systems Group
Applied Materials

Dr. Raman Achutharaman is corporate vice president of strategy and marketing for the Silicon Systems Group at Applied Materials, Inc., which comprises the company’s entire portfolio of semiconductor manufacturing systems. Dr. Achutharaman is responsible for defining the strategic plan to strengthen the company’s leadership in its core wafer fabrication equipment markets and effectively communicating the company’s vision and success to stakeholders.

Dr. Achutharaman rejoined Applied Materials in Oct 2010 from Solyndra LLC, a thin film photovoltaic startup, where he served as the senior vice president of technology and was responsible for thin film process and equipment technology, packaging, product design and transition from concept to high volume manufacturing. Prior to Solyndra, Dr. Achutharaman was at Applied Materials for 11 years in various roles of increasing responsibilities, most recently as general manager of the Rapid Thermal Processing product unit between 2003 and 2006.

Dr. Achutharaman received his undergraduate degree in metallurgical engineering from the Indian Institute of Technology, Chennai, India and his doctorate in materials science and engineering from the University of Minnesota. He has published more than 20 papers, review articles, and book chapters, and has received more than 8 patents.

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Jim Aralis

Jim Aralis Chief Technology Officer and Vice President, R&D
Microsemi Corporation

Jim Aralis has served as chief technology officer and vice president of R&D for Microsemi since January 2007. He has more than 30 years' experience in developing custom analog device and process technologies, analog and mixed-signal ICs and systems, and CAD systems.

Jim played a key role in transitioning Microsemi to a virtually fabless model, supporting multiple process technologies including, high voltage and high power BCD/CMOS, high power high integration CMOS, GaAs, SiGe, IPD, RF CMOS SoI, GaN, SiC, and several high-density packaging technologies.

From 2000 to 2007, Jim established and served as senior design director of Maxim Integrated Products engineering center in Irvine, Calif. Before that, he spent 7 years with Texas Instruments/Silicon Systems as mixed-signal design head and senior principal engineer. Additional experience includes 11 years with Hughes Aircraft Company in positions of increasing responsibility including senior scientist.

Jim earned a bachelor of science degree in Math Applied Science and Physics and a master of science in electrical engineering from UCLA. He holds 9 patents for circuit and system design.

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Mr. Paul Boudre

Paul Boudre Chief Operating Officer
Soitec

As Soitec Chief Operating Officer, Paul Boudre's responsibilities cover industrial operations, business development, strategic marketing, R&D, quality, procurement, and IT for all businesses. He joined the company in 2007.

A semiconductor-industry veteran of more than 30 years, Mr. Boudre gained extensive international experience through his previous positions managing industrial operations for IBM Semiconductor, STMicroelectronics, Motorola Semiconductor, and Atmel. From 1997 to 2006, he managed European operations for KLA-Tencor, one of the world's top five semiconductor equipment manufacturers. He was subsequently appointed Vice President for both the US and Europe.

Mr. Boudre holds a graduate degree in chemistry from France's Ecole Nationale Suprieure de Chimie de Toulouse.

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Mark Brillhart

Mark Brillhart Vice President, Technology & Quality
Cisco Systems Inc.

Mark Brillhart leads Cisco's Technology and Quality organization, a global team responsible for delivering customer-driven quality and reliability solutions and infrastructure for Cisco products. The team is committed to driving a competitive advantage for Cisco by ensuring innovation and excellence in manufacturing technology, test and component engineering, NPI, and closed-loop quality management.

With 300+ employees in locations around the world, Brillhart oversees a team responsible for developing industry-leading testing tools and technologies for leading-edge ASICs, PCBs, optical devices, custom memory modules, and complex interconnect technologies. Under Brillhart's direction, the Technology and Quality team owns key initiatives and functions – including Autotest, Green manufacturing, and Quality Excellence – that champion improvements throughout the manufacturing process and extend visibility and collaboration deeper into the global supply chain, while continuously raising the bar on quality.

Brillhart joined Cisco in 1999, first as a technical lead and then as manager of the Interconnect Reliability and Electronic Packaging teams. He has also served as Director of Hardware Reliability, Sr. Director of Component Quality and Technology, and Vice President of Manufacturing Operations Engineering. Brillhart has driven numerous cross-functional teams and initiatives, and has also led the Technology Council Roadmap team and the Process Development team.

In addition to his current responsibilities, Brillhart sits on Cisco's Federal Business Council and is a member of IEEE's CPMT Society. Prior to Cisco, he held a variety of engineering and technical lead positions at HP, as well as research and development positions in the medical products industry.

Brillhart has Bachelors and Masters degrees in Civil Engineering from University of Illinois, along with a Masters in Polymers from MIT where he was the recipient of the NASA Graduate Research Award and a Department Graduate Fellowship Award. A widely published author and speaker on process and materials engineering, Brillhart has also earned ten US patents primarily in the fields of surgical devices and assembly processes. Mark lives in Palo Alto with his wife and two children, frequently rides his Harley to work, and plays bass guitar in a blues-rock band.

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Dr. Roawen Chen

Roawen Chen Vice President of Manufacturing Operation
Marvell Semiconductor, Inc.

Dr. Roawen Chen joined Marvell Semiconductor in 2000, and promoted to Vice President of Manufacturing Operation, in 2005, where he is responsible for foundry management, global planning, and silicon engineering operation. From 2007 to 2009, Dr. Chen took on the additional role of Vice President and General Manager for Connectivity Business Units, and later expanded his responsibilities to leading Communication and Computing Business Unit, managing the product lines of Ethernet connectivity IC, mobile communication and application processor, and power management ICs.

Prior to Marvell, Dr. Chen held technical position in TSMC and Intel Corp. Dr. Chen holds a Bachelor of Science degree in Physics from National Tsing-Hua University and Ph.D. degree in Electrical Engineering and Computer Science from UC-Berkeley.

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Shung Chieh

Shung Chieh Vice President, Technology Development
Aptina Imaging

Shung Chieh is the Vice President of Technology Development and is responsible for the development of underlying pixel, process (including color filter arrays), and camera systems technologies for Aptina. Shung was most recently the VP of Engineering at Fairchild Imaging where he oversaw sensor, camera, image processing development and application engineering. Prior to Fairchild Imaging, he held various technical and management roles with the CMOS imaging business in Agilent Technologies and later Avago Technologies. While at Agilent and Avago, he oversaw the development of CMOS sensors and test chips, SOC's, and pixel technology as Director of R&D. He also joined Micron Imaging (now Aptina) for a brief time through the Avago acquisition. Dr. Chieh earned a BASc degree in Computer Engineering from the University of Waterloo and a Ph.D. in Electrical Engineering from Cornell University. He also holds an MBA from the Wharton School at the University of Pennsylvania.

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Matt Crowley

Matt Crowley Vice President, Hardware Development
Tabula, Inc.

Matt Crowley has served as Vice President of Hardware Development at Tabula since March 2007. In this role Matt drives all hardware development activities, broadly encompassing architecture thru silicon implementation. He has played a key role in the company's successful development and deployment of ABAX, its first generation of 3PLD products, and subsequent product development roadmap.

Prior to joining Tabula, Matt served as Vice President of 3D Memory Development at SanDisk Corporation. In this role he drove all aspects of 3D product and technology development focused on both one-time-programmable (OTP) and rewritable nonvolatile memories. Matt came into SanDisk by way of its acquisition of Matrix Semiconductor, where he served as Vice President of Product Development and oversaw the successful development and commercialization of two generations of novel monolithic 3D OTP memories.

Before Matrix, Matt held staff engineering and management positions at AMD/NexGen where he contributed to the successful K6, K7, and K8 processor lines. Matt started his career as a design engineer at Amdahl Corporation.

Matt received a Bachelor of Science degree in electrical engineering from the University of Illinois at Urbana-Champaign. He holds over 15 U.S. patents.

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Mr Joël Hartmann

Joël Hartmann Corporate Vice President of STMicroelectronics, Front-End Manufacturing and Proc
STMicroelectronics

Joël Hartmann is Corporate Vice President of STMicroelectronics, Front-End Manufacturing and Process R&D, Digital Sector, and has held this position since February 2012. He is also responsible for the Company's manufacturing operations in Crolles, France.

From 1979 to 2000, Hartmann worked at CEA-Leti, a premier applied-research center for microelectronics, information and healthcare technologies in Grenoble, France. In 2000, he joined STMicroelectronics as Director of the Crolles2 Alliance, the large-scale semiconductor manufacturing R&D initiative of STMicroelectronics, NXP and Freescale Semiconductor. In 2008, Hartmann was promoted to Group Vice President and Director of Advanced CMOS Logic & Derivative Technologies. In 2010, he gained additional responsibilities as a co-leader of the Semiconductor Research and Development Center in Fishkill, NY, within the IBM ISDA Technology Alliance for the development of advanced CMOS process.

Hartmann sits on the Board of the SOI Industry Consortium Initiative and is a Member of the IEEE Electron Device Society. He has filed 15 patents on semiconductor technology and devices and authored 10 publications in this field to date.

Joël Hartmann was born in Toulon, France, in 1955. He graduated from the Ecole Nationale Sup�rieure de Physique de Grenoble (ENSPG) with a degree in Physics.

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Prof. Chenming Hu

Chenming Hu TSMC Distinguished Chair Professor of Microelectronics
University of California, Berkeley

Dr. Chenming Hu is TSMC Distinguished Professor in Graduate School at UC Berkeley and a board director of SanDisk and was formerly the Chief Technology Officer of TSMC. He is known for his transistor reliability models, first industry standard SPICE model--BSIM, and 3D transistor--FinFET. A member of the national academies of US, China, and Taiwan, he has received the IEEE Andrew Grove Award, Solid State Circuits Award, and Nishizawa Medal, and UC Berkeley's highest honor for teaching--the Berkeley Distinguished Teaching Award.

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Dr. Subramanian S. Iyer

Subramanian S. Iyer IBM Fellow and Chief Technologist, Microelectronics Division
IBM

Subramanian S. Iyer is IBM Fellow and Chief Technologist at the Microelectronics Division, IBM Systems & Technology Group, and is responsible for technology strategy and competitiveness, embedded memory and 3 dimensional integration. Until recently he was Director of 45nm CMOS Development. He obtained his B.Tech in Electrical Engineering at the Indian Institute of Technology, Bombay, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles. He joined the IBM T. J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group until 1994, when he founded SiBond LLC to develop and manufacture Silicon-on-insulator materials.

He has been with the IBM Microelectronics Division since 1997. Dr. Iyer has received two Corporate awards and four Outstanding Technical Achievement awards at IBM for the development of the Titanium Salicide process, the fabrication of the first SiGe Heterojunction Bipolar Transistor, the development of embedded DRAM technology and the development of eFUSE technology. His current technical interests and work lie in the area of 3-dimensional integration for memory sub-systems and the semiconductor road map at 22nm and beyond. He holds over 40 patents and has received 24 Invention Plateau awards at IBM and is a Master Inventor. He received the Distinguished Aluminus award from the Indian Institute of Technology, Bombay in 2004.

Dr. Iyer has authored over 150 articles in technical journals and several book chapters and co-edited a book on bonded SOI . He has served as an Adjunct Professor of Electrical Engineering at Columbia University, NY. Dr. Iyer is a Fellow of IEEE and a Distinguished Lecturer of the IEEE and Chair of the mid-Hudson chapter of the Electron Device Society. In 2011 he received the Asian American Engineer of the Year award. He is the recipient of the 2012 IEEE Daniel Nobel award for emerging technologies. In his spare time, he studies Sanskrit and role of Indic languages, traditions and culture in different parts of the world.

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Subramani Kengeri

Subramani Kengeri Head of Advanced Technology Architecture, Office of the CTO
GLOBALFOUNDRIES

Subramani Kengeri is responsible for defining competitive process architecture on advanced nodes in support of "first time right" technology development. He is responsible for determining the technology feasibility, competitiveness and manufacturability of all elements of technology platform and to establish the advanced technology roadmap for GLOBALFOUNDRIES.

Subramani joined GLOBALFOUNDRIES in 2009 as the Vice President of Design Solutions responsible for World-wide Design Engineering & IP eco-system. He implemented strategic design enablement initiatives and established a strong foundation for collaboration with ARM, before moving to focus on R&D. He started his career at Texas Instruments and prior to joining GLOBALFOUNDRIES, he was the Senior Director of Design and Technology Platform at TSMC.

Subramani holds a master's in electrical engineering from Indian Institute of Technology (IIT, Delhi) and has been issued 30+ U.S. patents.

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Liam Madden

Liam Madden Corporate Vice President, FPGA Development and Silicon Technology
Xilinx, Inc.

Liam Madden is corporate vice president of FPGA Development and Silicon Technology at Xilinx. He has responsibility for FPGA design, Advanced Packaging (including Stacked Silicon Interconnect) and Foundry Technology. Madden joined Xilinx in 2008, bringing more than 25 years experience in a range of design and technology leadership positions with Digital Equipment Corp., MIPS Technologies, Inc., Microsoft Corp. (XBOX Division), and AMD.

Madden earned a BE from the University College Dublin and a MEng from Cornell University. He holds five patents in the area of technology and circuit design.

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David McCann

David McCann Senior Director, Packaging R&D
GLOBALFOUNDRIES

David McCann is the Senior Director of Packaging R&D at GLOBALFOUNDRIES in Malta, New York. In this role, Dave is responsible for Packaging R&D and back-end strategy and implementation.

David started at GLOBALFOUNDRIES in 2011. Prior to GLOBALFOUNDRIES, David worked at Amkor Technology for 11 years, most recently leading the BGA, Flip Chip and MEMS product groups. He was responsible for extensions of package technology, bump, applications, and business performance. Prior to this, Dave was responsible for the fcBGA and fcCSP business group at Amkor. He led cross-functional teams in various areas including networking product strategy, mobile product development, large die/lead free flip chip development, and wafer level product strategy. David worked closely with Amkor factories in Asia.

Prior to Amkor, David worked at Biotronik, GmbH in Portland, OR. Biotronik is a developer and manufacturer of implanted medical devices including defibrillators and pacemakers. David worked at Biotronik for 9 years and had various roles in Production, Process Engineering, Product Engineering, and Flip Chip implementation. His last role at Biotronik was leading the assembly, interconnect, and product transition from wire bond to flip chip.

David has supported the Electronic Component and Technology Conference for more than 10 years. This year he is Conference General Chair.

David McCann received his Masters in Engineering Management from the University of Santa Clara in 1985 and a BS in Ceramic Engineering from the University of Illinois in 1981.

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Steve Pateras

Steve Pateras Senior Director, Marketing, Silicon Test Division
Mentor Graphics Corporation

Stephen Pateras is the senior director of marketing for Mentor Graphics Silicon Test products. His previous position was VP Marketing at LogicVision. While at LogicVision Stephen also held senior management positions in engineering, and was instrumental in defining and bringing to market several generations of LogicVision's semiconductor test products. From 1991 to 1995, Stephen held various engineering lead and management positions within IBM�s mainframe test group. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada.

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Pushkar Ranade

Pushkar Ranade Senior Director, Process Integration
SuVolta Inc.

Pushkar Ranade is Senior Director of Process Integration at SuVolta. Prior to joining SuVolta in 2010, Pushkar was with Intel Corporation where he contributed to transistor process integration and development of Intel's 65nm, 45nm and 22nm logic technology. Pushkar joined Intel in 2003 after graduating with a Ph.D. from the University of California, Berkeley. At Berkeley, his research was in the area of sub-70nm CMOS transistor design and involved the integration of novel gate materials and ultra-shallow junctions. He has authored or co-authored over 40 technical publications and holds 9 U.S. patents.

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Rich Rice

Rich Rice Senior Vice President, Sales & Engineering
Advanced Semiconductor Engineering, Inc. (ASE)

Rich Rice currently serves as Senior Vice President of Sales for ASE (U.S.) Inc., with responsibilities within the North America region. Appointed in 2003, Mr. Rice oversees sales and applications engineering support for ASE. With over 28 years experience in the semiconductor industry, he has held various engineering and business development positions at Amkor Technology and National Semiconductor Corporation. Mr. Rice serves in advisory roles for MEPTEC as well as the iMAPS Global Business Council. He holds a BS degree in Agricultural Engineering from the University of Illinois.

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Mr. Nick Yu

Nick Yu Vice President, Engineering, VLSI Engineering
QUALCOMM

Nick Yu is a Vice President of Engineering at Qualcomm's CDMA Technologies Division. He is currently responsible for setting Qualcomm's semiconductor technology road maps including wafer fab process node, back end interconnect and packaging technologies. He manages engineering teams that are involved with our supply chain partners on execution of the technology road maps for Qualcomm's chipset products. Nick has 18 years of experience with Qualcomm on low power wireless chipset and SoC development, including managing chipset design, advanced semiconductor technology, deep submicron circuit design and methodology development, advanced semiconductor R&D and packaging development. He is one of the architects of, and has participated in the definition and development of, many Qualcomm chipset products. Nick has an MSEE degree from Georgia Institute of Technology.

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