GSA 3D IC Working Group Meeting | October 24, 2012


The GSA 3D IC Working Group completes their 2012 meeting schedule with a focus on 3D IC testing.  The working group will focus on deliverables, such as 3D IC Business Models, at the conclusion of presentations.

Please join us at Advantest on October24th, at 1:30 PM (PDT), as we continue to explore pertinent topics impacting 3D IC product development, adoption, and production.

Date and Location

Date: October 24, 2012
Location: Advantest
3061 Zanker Rd.
San Jose, CA 95134


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Webcast Information:
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Participant Passcode: 842 910 4881




Time Agenda Item  
1:30 p.m.

Opening Remarks, Ken Potts, Director of Marketing, Strategic Industry Alliances, Cadence

Ken Potts
1:40 p.m.

Gary Fleeman, Director Business Development, Advantest
2.5 & 3D Production Test: Getting to Known Good Die, Known Good Stacks

Coming 2.5D and 3D products pose new challenges to the production test environment. Providing a commodity viable 3D product demands implementation of unique test and handling solutions. Yield is the foremost concern but cost sensitivity and test economics are critical to any successful commodity. Manufacturing (back end) flows and new insertion points will be described. The presentation will also outline challenges of 2.5D and 3D implementation, highlight limitations with today's monolithic solutions, and offer alternatives for a high yield, integrated Die Level Handling environment.

Gary Fleeman
2:10 p.m.

CJ Clark, CEO, Intellitech
3D IC Test Standards Update

This presentation covers the activities in P1838 and P1149.1-2012 that support DFT architectures for 3D-SIC test.  IEEE 1149.1-2012 includes new support for describing and operating on IEEE 1500 architectures.   IEEE 1500 is frequently used for IC test.   IEEE 1149.1 support of IEEE 1500 creates an important link for minimal contact 3D-SIC product life-cycle test.  IEEE P1838 appears to be converging, at the time of this writing, on the presenter's recommendation for a mix of IEEE 1500 and IEEE 1149.1 architectures for 3D stacks.   Additional, non-detailed information will be presented on JEDEC HBM, WIO2 and LPDDR4 stackable memory standards in development.

CJ Clark
2:40 p.m.

Working Group Discussion

This session will include interactive discussion of presentations, topic discussion for future meetings, and other pertinent topics.

3:30 p.m.

Wrap Up