Developing Diverse Technology Solutions that Support Multiple Application Areas

Samir Chaudhry, Manager, Device Modeling, Jazz Semiconductor, a Tower Group Company
Ramesh Ramchandani, Director, Marketing, Jazz Semiconductor, a Tower Group Company
Shye Shapira, Director, RD Power Management Platforms, Tower Semiconductor
Ofer Tamir, Director, CAD and Design Enablement, Tower Semiconductor

Analog-intensive, mixed-signal (AIMS) ICs are defined as chips with a large analog content and a small digital content, and are designed for applications ranging from precision analog to high-performance radio frequency (RF) transceivers in communication systems. In this article, the process technology needs for AIMS ICs, from both the designer and the foundry perspective, are presented.

Over the last decade, the technology needs of AIMS ICs have diverged from those of digital ICs. As illustrated in Figure 1, the AIMS IC technology migration towards advanced nodes (sub-130-nanometer) has been slow. Instead, the need for higher performance analog components, such as SiGe bipolars, high-voltage metal-oxide semiconductor field-effect transistors (MOSFETs) and high-performance passives, coupled with the need for lower development costs, has necessitated the use of specialty process technologies at mature nodes.

Figure 1. Scaling Trends for AIMS vs. Digital ICs

AIMS IC Supplier Technology Needs

From an AIMS IC supplier perspective, end-application needs dictate the technology selection process. Typically, the foundry group within a design organization evaluates available foundry options based on performance and cost. Key figures of merit for the various classes of AIMS ICs are shown in Table 1. For all applications, the requirements span multiple columns. For example, cellular transceiver ICs require high speed, low noise, high linearity, good matching, and high-quality and density passives. This requires a careful evaluation of technology features, requiring foundry liaison groups to dig beyond the marketing material provided by the foundry. This can be accomplished by evaluating benchmarking circuits, such as low-noise amplifiers (LNAs) and phase-locked loops (PLLs), using the process design kits (PDKs) provided by the foundry.

For high-risk designs, evaluation circuits should be fabricated and tested on dedicated or shared silicon runs (“pizza” or multi-project wafer shuttles). Once the performance needs have been defined, the cost trade-off optimization needs begin to be addressed. A modular foundry offering with capabilities to add/delete modules on/off a superset offering will allow the user to truly maximize the cost/performance trade-off. For short-lifespan products, prototyping costs can significantly impact the final cost of an IC. In these cases, the availability of relatively cheap, shared “pizza” shuttles is critical. Given that the path to a production mask set may need two or more iterations, AIMS foundry offerings based off mature nodes will significantly reduce the mask and production expense.

Table 1. Device-Level Performance Needs for AIMS ICs

The level of subsystem integration on a single chip is a critical decision for most design teams. A mobile communication system offers a good case study in illustrating the integration vs. specialization trade-off. Two separate factors have prevented the complete integration of a “phone on a chip,” using either SiGe BiCMOS or advanced RF CMOS nodes (e.g., 65-nanometer). First, the inability of standard CMOS to support high operating power or switch isolation needs has prevented a true CMOS front-end module (FEM), while the high-speed and density needs of the digital baseband prevent implementation in the relatively slower CMOS available in SiGe BiCMOS offerings. Second, the best-of-breed requirements of each subsystem necessitate implementation of the system via two or more chips. Depending on the application, the transceivers are either being implemented in SiGe BiCMOS or 65-nanometer RF CMOS offerings. The cost/performance trade-off for the digital signal processor requires a technology shift from 65-nanometer to 45-nanometer CMOS. The FEM ICs are predominantly GaAs or SiGe Bipolar implementations.

Figure 2. Block Schematic of a 3-4G Mobile Communication System

Adapted from¹

AIMS IC Foundry Perspective

From an AIMS IC foundry perspective, a dedicated understanding of evolving customer needs is an important factor when developing new technologies. It is apparent from Table 1 that developing technologies specific to each AIMS application regime is neither practical (e.g., the last three rows show that there are practically infinite combinations of needs) nor a necessity. Instead, a limited number of superset offerings targeting specific device-level performance criteria are sufficient in enabling products across a wide application spectrum. A representative superset offering for RF and power management ICs is shown in Table 2. Each row represents a modular component that, ideally, can be added or removed when “dialing in” a custom process.

In the RF domain, multiple flavors of SiGe bipolars allow integration of diverse functionality on the same chip while allowing custom IC developers to select a single NPN to reduce cost, should the added functionality be redundant. The option to eliminate thin-gate CMOS can be exploited in applications where a lower performance MOSFET can be shared for digital and input/output (I/O) functions. High-performance/density passives and the ability to choose the number of layers in a metal stack allows design teams to maximize the cost/performance trade-off. In the power domain, high-voltage MOS devices essentially replace SiGe NPNs to create a parallel superset technology. Other key differentiators in the power offering are non-volatile memory for consumer applications and moderate performance Si bipolar junction transistors (BJTs) for integration of analog functionality. Device reuse across the diverse application space is also evident from Table 2 and is essential in defining foundry roadmaps. Superset technology offerings reduce development and support overhead for foundries and allow them to pass the reduced costs to customers.

Table 2. A Representative Superset Offering for RF and Power Management ICs

The table above illustrates how the same device can be shared across the application space.

Design Enablement

An often overlooked consideration by design teams while evaluating AIMS technology platforms relates to design automation. Design enablement tools, including silicon-verified device models and flexible design environments, allow IC design teams to test, modify and improve the functionality and yield of new products long before the first prototype is manufactured. This is done in the environment in which the end product will be used, and includes advanced modeling of parasitics that can significantly degrade performance. Design enablement tools for AIMS ICs can be classified into three categories:

• Front-End Modeling: The need for accurate front-end models is essential for AIMS ICs, where the performance trade-offs extend to multiple dimensions. This is in contrast to digital ICs, where optimization is typically limited to speed and power consumption. In a mobile communication system, for instance, the active devices’ gain must be optimized vis-à-vis linearity, noise and power consumption. Advanced front-end models, such as PSP² (surface potential-based MOS model) for MOSFETs or HICUM³ (high-current model) for NPNs, allow for accurate modeling of active devices. For high-power applications, modeling thermal effects is critical. Advanced characterization capability using pulsed systems allows accurate self-heating models to be developed. Likewise, accurate high-frequency models for inductors and varactors are vital to ensure first-time success for RF ICs.
   
• Physical Design Enablement: Beginning with scalable models and p-cells and extending to accurate extraction of layout parasitics, physical design enablement capability allows a designer to optimize a device’s performance across the geometry space. Modeling isolation modules, such as triple-well, deep-trench or SOI layers, aids in the optimization of device size for noise performance. Without these capabilities, designers often end up over designing, which leads to larger die sizes.
   
• Statistical Modeling: Process variation is inherent in any fab. Digital design has long relied on fast, typical and slow corners to evaluate the impact on a circuit’s yield. These corner models typically target digital-centric figures of merit, such as speed and power consumption, and have limited use for AIMS designs where the targeted figure of merit is not known to the modeling engineer. A statistical model, which mimics the random variation of independent process variables in a fab, is the most accurate method of simulating process variation. Statistical model extraction techniques, such as backward propagation of variance (BPV), allow models to align with fab statistics⁴.

Conclusion

Low cost, performance, integration and modularity are critical requirements for AIMS foundry technology offerings. Managing costs, during both the prototyping and production phase, is vital in enabling low-cost ICs in consumer markets. Foundry technologies that offer sufficient performance trade-offs (e.g., on-resistance or speed vs. breakdown) allow IC designers to optimize and enable multiple subsystems on the same chip. Low-cost, yet solid performance offerings will often prevail over high-cost, high-performance offerings. Highly integrated modular offerings are important in allowing foundries to develop, qualify and offer superset technologies to support a wide spectrum of IC applications, and in allowing IC design teams to customize the technology feature set at the lowest cost. To reduce time-to-market and prototyping costs, best-in-class design automation tools are essential.

About the Authors

Dr. Samir Chaudhry leads Jazz Semiconductor’s modeling activities. His research interests include RF CMOS and statistical modeling. Prior to joining Jazz, he was a Distinguished Member of Technical Staff with Bell Labs, where he worked on technology computer aided design (CAD) and device modeling for scaled silicon technologies. Based in Newport Beach, California, Samir can be reached at samir.chaudhry@jazzsemi.com.

Ramesh Ramchandani leads the marketing effort at Jazz Semiconductor. Previously, he was president and COO of InPlay, a consumer products company. He also has served in various management positions, including VP/GM of ON Semiconductor, EVP of ZiLOG and director of marketing for Celeritek. Based in Newport Beach, California, Ramesh can be reached at ramesh.ramchandani@jazzsemi.com.

Dr. Shye Shapira manages power management research development (RD) at Tower Jazz. Prior to working at Tower, he was at Agere, Lucent-Bell Labs and was a research associate at the University of Cambridge. Based in Israel, Dr. Shye Shapira can be reached at shyesh@towersemi.com.

Ofer Tamir has led the design enablement department at Tower Semiconductor for the last six years. He has more than 20 years experience in electronic design automation (EDA) and design flows developing and supporting EDA tools. Prior to Tower, he led the CAD group at DSPG and was with National Semiconductor. Ofer is based in Israel and can be reached at oferta@towersemi.com.

Resources

¹H. Bennett, et al, IEEE TED, July 2005.
²G. Gildenblat, et al, “PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation,” IEEE Transaction on Electron Devices, Vol. 53, No. 9, September 2006, pp. 1979-1993.
³HICUM Manual, http://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_doc.html.
⁴C.C. McAndrew, “Statistical Circuit Modeling,” SISPAD 1998.

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