Away from the Bleeding Edge Life is Good

Paul Double, Founder and Managing Director, EDA Solutions

To look at the many articles on rising IC design costs, one would think only a smattering of heavily funded start-ups and rich systems companies could ever afford to do application-specific IC (ASIC) design. Figures such as a $1 million plus to buy one mask set and $10 million to complete an IC design clearly position ASIC design as only a rich person’s game. However, these figures are only for leading-edge processes that are cost-justified by the ability to integrate tens of millions of transistors onto one die. But for analog and mixed-signal ICs, the picture can be very different, as is explained in the remainder of this article.

Despite the hype about rising costs, for many projects, ASIC design and production has not become more expensive over the last 10 years, but has actually gotten cheaper – to the point that many people who previously believed field-programmable gate arrays (FPGAs) or structured ASICs were their only options are finding that the dedicated ASIC approach is more cost-effective, especially where the system requires analog. The key is to choose the appropriate design tools and process, taking advantage of its maturity to deliver cost savings.

Mask costs seem to go up all the time, but that is only true across process nodes, and most of the increase is associated with the need for enhanced mask techniques associated with sub-wavelength lithography for sub-0.13-micron processes.

In fact, mask costs do fall over time. Mask makers obtain more experience with processes as time goes on, resulting in cheaper masks for a given process. Most of the savings are made in the first few years, but it is commonplace for mask-making costs to continue to fall in subsequent years.

Although billions of dollars go into expanding fab capacity at the leading edge every year, many chipmakers still have acres of silicon going through fab lines that are five, 10 or even 20 years old. These fabs cost comparatively little to run and have the benefit of being fully depreciated. This means that the fab owner is no longer paying for fab equipment. Most fab owners depreciate or write-off the purchase cost of their equipment over a five-year period. In effect, once this five-year period is over, the equipment has been paid for. All the fab owner needs to take account of are the running costs such as staffing and materials.

Many companies take advantage of these older processes to make a wide variety of devices. The industry statistics body Semiconductor International Capacity Statistics (SICAS) provides information on the available capacity for each process node and its utilization since 1994. The capacity is measured in terms of 8-inch wafer equivalents. This makes it easier to compare the capacity available on older mixed-signal processes that may use 4-inch or 6-inch wafers instead of the mainstream 8-inch and, increasingly important, 12-inch wafers.

As each new process node takes off , SICAS’ statistics show that some older capacity is shut down. But chipmakers have chosen to maintain substantial capacity even for older 0.80-micron and 1.0-micron processes. And these lines have significant utilization. In the last available report, even lines running processes with geometries larger than 0.70-micron demonstrated utilization around 80 percent. This is profitable for fab owners and not at a level where it is too scarce to be cost-effective for users.

Nearly half of the 8-inch wafer equivalents shipped today is on processes that were introduced more than five years ago. Out of the 24 million wafers shipped in the third quarter of 2008, more than 9.45 million were on 0.13-micron or older processes. Indeed, wafer production capacity on some of the cheapest processes, such as 0.50-micron and 0.70-micron, outstrips the popular 0.18-micron process capacity. A 12-quarter summary of SICAS’ data showing the relative capacities for various ASIC technologies is illustrated in Figure 1.

Figure 1. Wafer Capacity by Process Geometry

Source: SICAS

As well as production costs, design costs for those working on older processes have improved, particularly for those working on mixed-signal flows. Most of the risk in analog IC design lies in uncertainty. When processes are first rolled out, they offer a moving target to the analog engineer. Key process parameters may shift dramatically from batch to batch as the engineers tweak settings to improve overall yield. This makes it difficult to model analog circuits. However, once the process has bedded in, the foundry can make available accurate libraries that reflect the behavior that engineers will see in the real silicon, reducing design risk. These improvements are realized in foundry-specific process design kits (PDKs). These are offered by foundries, multi-project wafer (MPW) service providers and tool vendors alike, and the more they are used, the better they become.

The use of older processes brings tool costs down too. There is no need to buy expensive leading-edge design tools intended for advanced 45-nanometer system-on-chip (SOC) design, as they contain many features that are unnecessary. For example, routers in high-end tools contain algorithms to calculate for the effects of wire length on the speed of circuits. However, these calculations are unnecessary for 0.35-micron and older processes where wire length is less critical than gate speed in determining the speed of operation.

Furthermore, many of the older processes use fewer metal layers than the leading-edge processes in use today. Four levels of metal or fewer are commonplace in 0.35-micron and older processes. As these older processes offer support for relatively high-voltage operation, unlike the 0.25-micron and 0.18-micron processes, they are common choices for mixed-signal designs where analog accuracy is important.

Costs and risks in mask and wafer production can be further reduced by using MPW services from companies such as MOSIS. Where small quantities of chips are needed for evaluation, or for small production runs, several designs are incorporated into a single mask set, as shown in Figure 2, with individual customers only paying for the actual die area their devices occupy. Customers typically order 40 devices for evaluation before going to the expense of a dedicated mask set, but up to 1,000 devices of any one design can be produced in a single MPW run. Costs are only a fraction of those needed for single-device dedicated masks sets and wafers, and customers only pay for the proportion of the wafer that their devices occupy.

Figure 2. A MPW Reticle

Source: MOSIS

Most major foundries, including IBM and X-FAB, support MPW services. A variation on this theme offered by X-FAB is for several mask levels to be drawn on the same carrier. Figure 3 shows four layers on each mask, cutting mask costs by 75 percent.

Figure 3. The Multi-Layer Mask (MLM) Approach from X-FAB

It’s important to remember that neither older processes nor MPW services inhibit leading-edge analog design. The first single-chip Bluetooth transceiver was developed in 0.35-micron CMOS. More recently, when a Danish start-up was developing the next generation of signal-conditioning ASICs to fit inside microelectromechanical systems (MEMS) microphones for portable devices such as mobile phones and digital cameras, they did not choose 90-nanometer or 65-nanometer as one might expect for such high-volume, cost-sensitive applications. As the ASIC needed to offer high sensitivity, signal-to-noise performance and a digital output via an on-chip analog-to-digital (A/D) converter, the advanced analog design was implemented entirely in 0.35-micron CMOS. The low wafer cost coupled with excellent yield ensured the device offered sufficiently low pricing for the high-volume application.

Low-cost layout tools, such as Tanner EDA’s L-Edit, which was used extensively in both the above designs, support autorouting for up to three layers for digital designs and provide full support for analog designs, allowing engineers to move into mixed-signal chip design on mature processes cost effectively and easily.

On the analog side of the design, low-cost tools bring many of the benefits that high-end tools offer without unnecessary features. Low-cost tools are often easier to learn because they do not place advanced features in the way. However, this does not mean they do not have the ability to support the engineer. In any tool flow, it is important to have built-in support for custom automation. This can bring engineering time and cost savings on designs that repeatedly reuse common features and circuit types. Mixed-signal designers will often design similar circuits for different ICs or different cores for the same IC such as phase-locked loops (PLLs) that drive different digital bocks. Laying them out polygon by polygon each time is a tedious process. Luckily, low-cost tools still provide scripting and programming interfaces that are equally as effective as those found in high-end, mixed-signal tools.

For example, many IC designers have used the macro programming interfaces in L-Edit to implement libraries of functions that automate the job of generating multi-fingered transistors, such as those shown in Figure 4, and other complex shapes that would take a long time to draw by hand. T-cells, being object-oriented, make it possible to build complex hierarchies of circuit elements that can be parameterized and generated quickly before being tuned by the experienced hand of the designer.

Figure 4. A MOSFET Layout Auto Generated by a Parameterizable Cell

When it comes to stitching together the various blocks of a chip design during top-level chip assembly, it is important to have an effective full-custom layout tool. But it does not have to be a dedicated high-end tool. There are cost-effective, full-custom layout tools available that are up to the job, and many mixed-signal IC designers have used them effectively. Again, the widespread support for Graphic Data System (GDS) II means that a company does not have to resort to proprietary unified databases used by high-end tools to perform chip assembly. Good practices in partitioning and port naming are far more effective than complex, dedicated chip assembly tools.

A low-cost tool has one further saving on its side. Ongoing support costs form a major feature of high-end tools. High-end tools are often designed for large, often geographically separated, design teams. To deal with the complexities of such an environment often demands the support of a dedicated computer aided design (CAD) department or the involvement of expensive maintenance contracts. If a company is working with a smaller mixed-signal design team, it must ask itself whether it needs to incur the cost of this type of CAD support, especially when more cost-effective tools are designed to work straight out of the box.

For mature processes, IC design is becoming more accessible thanks to the readily available production capacity and lower non-recurrent engineering costs made possible by low-cost tools and lower priced masks. There is no need to feel that FPGAs or structured ASICs and board-level analog circuits that cannot be squeezed onto these digital-only parts are the company’s only options. Mature processes allow a company to save costs and improve performance by putting the key differentiating elements of a product design on one IC. Custom ICs are no longer the preserve of those companies with deep pockets.

About the Author

Paul Double is EDA Solutions’ founder and CEO. After gaining a B.S. (Hons) in physics and electronics at the University of Warwick, UK, Paul started his career in IC design with Phillips Semiconductors (now NXP), eventually moving into product management. Paul then spent eight years in design consultancy and electronic design automation (EDA) software sales management, first with Rood Technology, then later with Acapella. It was at Acapella that Paul first gained experience with Tanner’s tools and came to fully appreciate the benefits of MPW services. In 2001, Paul founded EDA Solutions to further the interests of both Tanner and MOSIS throughout Europe. In this time, Tanner’s sales in Europe have more than tripled, with Tanner now a serious rival to the leading analog design tool providers. EDA Solutions is a strong supporter of GSA activities in Europe, with Paul on the steering committee of this year’s Semiconductor Executive Forum in Munich. You can reach Paul Double at +44 (0)1489 564253.

Back to Articles Home