Why Logic Foundries Will Fail in Moving to
Analog
Jens Kosch, Chief Technology Officer, X-FAB Silicon Foundries
Volker Herbig, Marketing Manager, X-FAB Silicon Foundries
The analog foundry business is not a fad. Many foundries
are seriously trying to move into this space. However,
transformation requires a change from being contract
manufacturers that provide capacity and compete on the cost side,
to becoming true providers of feature-rich process technologies
with modular front- and back-ends and comprehensive process
characterization. Also, analog foundries must offer a complete
analog design ecosystem including libraries, analog intellectual
property (IP) and lots of design support – complicated by the
absence of standards. Such capabilities would enable customers
to reuse their analog IP across different applications and various
technology platforms. Moving into the analog space is no easy task,
and such a transformation, especially near term, is barrier-ridden.
Figure 1. Analog Design Ecosystem
Analog foundries must offer a complete analog design ecosystem including a large variety of active and
passive primitive devices, digital standard cell and input/output (I/O) libraries, analog IP, models and
comprehensive design support.
Why is there so much activity in the analog foundry space right
now? It’s commonly perceived that the digital business is driven by
Moore’s Law, which states that the number of gates doubles every 18 to
24 months. The implication is that whoever follows Moore’s Law must
move to smaller process nodes. Currently, 22-nanometer nodes are in
development. However, the associated costs are rising significantly,
making it more and more difficult to justify such investments when
only a handful of applications (e.g., microprocessors, baseband chips
for cell phones, DRAMs and Flash memory) create a positive return
on investment (ROI). Often, it’s no longer feasible to move to smaller
process node development. The number of players that can afford to
do business in the digital foundry space is shrinking rapidly. Such
players as TSMC, UMC and Chartered have the financial strength to
follow Moore’s Law, but it’s not known if they or other foundries will
be able to follow it in the future.
The accelerating cost associated with following Moore’s Law and
building 300mm mega-fabs capable of running up to 100,000 wafers
per month leaves a number of smaller digital foundry players at a
competitive disadvantage. They are stuck with 8-inch fabs and process
capabilities from 0.35- to 0.13-micron. The digital applications they
previously served are moving to 90-nanometer and smaller geometries
manufactured in highly efficient 300mm fabs, well beyond the range
these smaller fabs can handle. Therefore, these foundries face the
challenge of trying to sustain profitability.
The way out of this dilemma is to address applications within
their technology reach such as CMOS image sensors, smart discretes,
CMOS microelectromechanical systems (MEMS) or analog
applications.
Analog is the largest market at approximately US$40 billion in
2008. It’s no surprise that many smaller foundries are trying to find
new business in the analog fab space.
Although analog IC vendors follow Moore’s Law, they follow it
at a much slower pace, and do not jump to different process nodes
every 18 to 24 months. In fact, major analog nodes of 1.0- , 0.80-,
0.60- and now 0.35-micron are in stark contrast to the digital nodes
currently at 45-nanometer, already nearly an order of magnitude
smaller.
Analog IC vendors currently are moving to 0.18-micron, with
0.13-micron analog technology in development. However, many
analog integrated device manufacturers (IDMs) have internal
capabilities down to 0.35-micron only. To move to quarter micron
and below to remain competitive, they face a major decision: build
their own 0.18-micron capabilities (i.e., build a new fab) or choose a
foundry partner with these capabilities.
So the semiconductor industry finds itself at an unusual nexus.
Second-tier digital foundries are stuck with idle capacity for process
nodes at 0.35-, 0.18- and 0.13-micron, and are looking for ways to
fill it. Meanwhile, the analog world now is moving into those process
nodes, leaving many analog IDMs that lack this capability facing
“build or buy” decisions. The situation is heightened by the pressure
of the industry-wide move toward fabless or fab-lite strategies, and
the extremely difficult task of choosing the right analog foundry
partner.
Wide Arc of Technology and Applications
The term “analog” is loosely defined, and therefore people have
different understandings of what “analog foundry” means. Analog designs, mixed-signal radio frequency (RF), and high-voltage (HV)
and power technologies covering those areas fall under the umbrella
of “analog” or “analog/mixed-signal,” and analog technologies can be
categorized as follows:
- Analog Designs (big A /little D): A digital signal is defined
at discrete values of time and amplitude (voltage). In contrast,
an analog signal is defined across a continuous range of time
and amplitudes. The real word is analog, not digital. Its signals,
whether a current, voltage, pressure or inertial signal, need to be
sensed and transferred to the digital domain for further digital
signal processing. Analog designs have a large amount of pure
analog circuits and a rather small amount of digital content.
Typical applications are sensor front-ends, analog/digital
converters (ADCs) and comparators.
- Mixed-Signal/RF Design: Mixed-signal/RF design typically is
used for applications in the RF range. It requires the integration
of digital circuits and fast, highly linear analog signal processing
used for receiver and transceiver circuits at frequencies higher
than 500Mhz. WLAN, Bluetooth and ZigBee radio applications
are typical.
- HV Technologies: Digital circuits are limited to their core and
I/O voltages that, depending on the process node, fall between
1.1V and 5V for the core and 3.3V and 5V for the I/O. In many
cases, higher voltages than that are required for applications
such as power management, power conversion and lighting.
Voltages can go as high as 700V for power net applications and
drive currents up 1A. Voltages between 5V and 40V are most
frequently used.
- Power Technologies: Power technologies handle HV and
high current at the same time, typically at process nodes of
0.60-micrometers and above. Fewer digital gates are integrated
in circuits that handle power, whose currents exceed those on
the HV side. Depending on the process architecture, currents
up to 20A peak are possible. The boundaries between HV and
power are somewhat fluid. Motor drivers, linear regulators and
lighting are typical power applications.
Many analog applications require the combination of analog
circuits, mixed-signal RF, HV and power, or a subset. Unlike the
digital world where only a few capabilities suffice, addressing analog
requirements calls for a wide range of different technologies.
Embedded non-volatile memory (NVM) capabilities are needed
for trimming, data or program storage. Process and design IP
architectures for embedded NVM are different for mixed-signal
applications than digital applications. For digital applications,
the embedded NVM blocks dominate the chip area that requires
a very dense memory cell. Even if this comes with more than five
additional layers, it is still cost-effective. For analog-dominated,
mixed-signal designs, it is important to have a low mask count NVM
solution available. The most complex functional integration would
be “logic+analog+HV+NVM,” which would add too many process
layers and would not be very cost-efficient. Therefore, a lean process
architecture for the full-functional integration of logic, analog, HV
and NVM is required.
Analog/mixed-signal devices often are required to work in a harsh,
unfriendly environment, where they must cope with significant
temperature differences, HV, switching noise or interference from
neighboring elements.
Table 1. Consumer, Industrial and Automotive Environmental
Requirements
Source: Robert Bosch GmbH, X-FAB
Consumer, industrial and automotive ICs must meet different environmental
requirements.
Automotive requirements are the most demanding.
Design Effort vs. Process Complexity Tradeoffs
From a process standpoint, analog technology must cover a larger
range of issues than digital. The digital world is primarily concerned
with process technology, with design support and IP taken care of by
third parties. In contrast, analog foundries focus on multiple process
technologies, process characterization and design support issues, as
well as solutions for the use of analog IP.
Analog/mixed-signal process technology encompasses digital,
analog, HV, RF and NVM elements – in many instances, all on the
same piece of silicon.
Figure 2. Analog/Mixed-Signal Process Technology
Analog/mixed-signal process technology requires integration of digital, analog, HV, RF and NVM
elements.
Depending on the application and end market, analog processes are
application-specific to serve high-volume applications cost effectively.
However, the lengthy and cost-intensive development of a new, dedicated
process often cannot be cost-justified because volumes are too low.
The best strategy for reconciling these demands is a modular
technology approach. The increased flexibility of the modular
platform allows product designers to select only those front- and
back-end modules they really need, guaranteeing the best possible
tradeoff between design effort and performance. Developing lean
process architectures that address all these sometimes conflicting
requirements is difficult, especially when integrating low on-state
resistance (RDSon) HV transistors with dense, low mask count
NVM is the main challenge.
Greater Challenges with Process Characterization
and Design Support
The digital world essentially relies on two basic devices, NMOS and
PMOS transistors. From the design perspective, devising digital
ICs is rather straightforward. The process is largely removed from
both technology considerations and the actual physics of the devices
because electronic systems are modeled using hardware description
language (HDL). In addition, place-and-route tasks and verification
is highly automated. Digital IC design typically is focused on logic
correctness, maximizing circuit density, and placing circuits so clock and timing signals are routed efficiently. As a highly automated
process – at least for technologies above 90-nanometer – it leads to
variable, fab-independent netlists and easily generated layouts that
usually are right the first time.
In contrast to digital design – in which only a few device parameters
such as threshold voltage, leakage and saturation currents need to be
considered – analog/mixed-signal design must cope with far more
complex specifications. The physics of the devices are a primary
concern. Parameters such as gain, matching, noise, voltage and
temperature coefficients, power dissipation, resistance and the analog/digital interface are especially crucial if there are different internal
supply voltages. Additionally, parasitic devices and effects, such as
crosstalk and substrate noise, and interface issues with the environment
(e.g., electromagnetic compatibility) are major design challenges. Each
device in the analog world must be carefully characterized and modeled
across a very large parameter space to ensure a reliable circuit design. A
wide range of statistical models is needed, such as worst-case models,
statistical corner models and Monte Carlo mismatch models, to enable
circuit design sizing and design-centering techniques that achieve high-yielding,
robust designs.
Extensive verification routines are crucial in the design flow to
guarantee the analog/mixed-signal design functions well, can be
manufactured and is reliable. These verification routines must include
safe operating area (SOA) checks for HV MOS transistors, pre- and
post-layout parasitic extraction, design rule checks (DRC), layout versus
schematic (LVS) routines and electrostatic discharge (ESD) checks.
In addition, the foundry must support a wide range of electronic
design automation (EDA) platforms, enabling designers to choose
best-in-class tools for optimizing their design flows. Setting up such a
comprehensive design support and process characterization ecosystem
is a major precondition for a successful analog foundry.
Although reusable IP is available on the digital side, reusing IP in
the analog world that deals more with the physics of the design is far
more difficult. It is necessary though for analog designers to be able to
reuse their IP to shorten design time, given the smaller volumes and
design complexity. One established solution for dealing with this type
of problem is having the foundry provide a wide range of analog IP
optimized for its processes. Analog IP provided by an analog foundry should comprise digital and I/O libraries, and analog building blocks
such as bandgap, bias cells and NVM macrocells.
Different Business Models
Beyond differences in the technical side, there also are differences
in the digital and analog business models. The digital world has
fewer designs, but high volume. Fewer process variants are seen,
and the designs are easily transferable between fabs. First-time-right
is standard, enabled by comprehensive EDA support. Abundant
transferable digital IP can help shorten the design process. Product
lifetime and availability are consumer driven, and are relatively short
compared to the analog world.
Analog foundry business leads to more tape-ins, and each one often
requires its own process variant. In contrast to digital designs, first-time-right
typically is not achievable. In addition, transfer from fab to fab
is quite difficult and requires substantial effort because the designs are
fab-specific. Again, that’s because analog designs must cope with much
more complex specifications and the physics of the devices, making fab
transfer extremely difficult. Extended product lifetime requirements –
in some cases up to 15 years – are typical for analog circuits.
Moving from Digital to Analog: Invitation to Fail
Compared to digital foundries, analog foundries must expand
their operations well beyond developing processes and providing
manufacturing capacity. They need to deliver extensive process
characterization data, analog IP and design support. And they must
support more customers with multiple small-volume designs. Multiple
re-spins lengthen development cycles to typically two years or more.
The analog design ecosystem provided by the foundry is intended
to help avoid redesigns and accelerate time-to-market. Product ramp
schedules of more than two years make business development a
lengthy process, requiring patience and financial strength.
With longer development and product lifecycles of up to 15 years,
analog foundries must be financially stable and have a sustainable
business model. These technical and business requirements, as well as
the amount of time and depth of expertise needed to transform from
a digital foundry model to an analog foundry model – both of which
the digital world lacks – make such a move an invitation to failure in
today’s already challenging business environment.
About the Authors
Dr. Jens Kosch, CTO and director of design support and technology development,
drives all technology directions for X-FAB Silicon Foundries, which focuses on
manufacturing silicon wafers for analog-digital ICs. Prior to X-FAB, Dr. Kosch
served as director of the design center at Thesys Gesellschaft für Mikroelektronik mbH.
He holds both a Master of Science and Ph.D. in electrical engineering from Ilmenau
Technical University, Germany, with a concentration in electronic components.
Volker Herbig is the technical marketing manager responsible for strategic business
model development at X-FAB Silicon Foundries. Previously, he held engineering,
marketing and management positions at Siemens, Inkjet Technologies and Carl Zeiss.
He holds a master’s degree in physics from Humboldt University, Berlin, Germany.
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