Foundry-Friendly Memory IP for Analog Trimming and Sensor Calibration

Jim Lipman, Director, Marketing, Sidense

Integrating third-party silicon memory intellectual property (IP) is not simple. While IP integrators are looking for turnkey IP solutions, problems caused by foundry differences at the same process node, difficulties associated with process scalability, and variability of both fabrication processes and analog circuits and sensors make “foundry-friendly” memory IP design for mixed-signal chips difficult.

This article discusses the requirements for analog trimming and sensor conditioning mechanisms, and describes the architecture and technology of a reliable, embedded non-volatile memory (NVM) that minimizes dependence on foundry-specific process steps. The field-programmable memory and support circuitry can be implemented in standard logic CMOS processes, is inherently scalable to leading-edge process nodes, and is very tolerant of process variability – a key consideration below 90-nanometers. When implemented in silicon, memory macros based on this technology provide an efficient mechanism for in situ digital calibration of analog sensors, such as those encountered in automotive and industrial applications, and for trimming analog circuitry to increase silicon yield.

Accommodating Multiple Foundries and Process Nodes

Today, designing a chip usually does not mean targeting the design for a single-source foundry at one process node. The design team should keep in mind that their (or “the”) chip may also be implemented in other foundries at some point to take advantage of cost savings, availability and, possibly, process features as well. Identifying and designing to accommodate a second foundry makes good business sense for negotiating prices and as a back-up if something interrupts the chip flow from the primary foundry.

Silicon foundries share many common features in the way they process silicon at a given process node. However, each foundry has its own “secret sauce” – design rule tweaks and process variations that optimize chip performance at a node – and these tweaks become more prevalent with shrinking processes. Such foundry-specific design-rule sets and process differences complicate the job of a silicon IP company that develops IP products for different chips that target different foundries.

Third-party IP developers must support multiple foundries so they can supply their products to customers who want to use several foundries. The simpler the process of redesigning and qualifying IP at multiple foundries, the faster these IP vendors can meet the needs of IP integrators who will be using multiple foundry sources.

OTP for Analog and Mixed-Signal Applications

Shrinking process nodes and the accompanying increase in on-chip functionality has resulted in a continuing rise of analog and mixed-signal circuitry placed on a chip. Furthermore, chip vendors are addressing the need for enhanced integration between what are designed as digital chips and the analog “outside world” (e.g., controllers that interface with analog sensors in automotive, industrial and other applications).

As chip operating frequency increases, it becomes harder to get wide operating ranges for critical analog IP cores such as voltage-controlled oscillators (VCOs) and frequency dividers. The fluctuations of circuit parameters caused by random and systematic variations in key manufacturing steps become more significant at 90-nanometers and below, and the process variation of circuit performance is one of the main concerns in high-performance analog design at advanced process nodes.

The expanded design space of an analog vs. a digital circuit means that, in general, embedded analog blocks demonstrate broader design parameter variability than do digital cores. To meet stringent design specifications, analog cores may require on-chip digital trimming operations. The trimming requirement becomes more important as process nodes shrink due to the increased variability of analog IP performance parameters at smaller processes. This manifests itself as increasing yield loss when chips with analog IP migrate to smaller process nodes since a larger percentage of analog blocks on a chip will not meet design specifications due to variability in process parameters and layout.

Typical applications for analog and radio frequency (RF) circuits include wireless communications, video and graphic displays, image sensors and power management chips. It is important to be able to adjust analog blocks on these types of chips to enhance yield and improve profitability of the products in which these chips are used. The variations caused by process and layout variations in RF circuits, image sensor cells and display pixels must fall within critical design ranges, or else the systems using these types of chips can’t be used. In many cases, this can be a very expensive proposition, for example, for a large video display. One-time programmable (OTP) trimming is used to increase the yield of image sensor, display controller and RF chips, thus increasing overall product profit margins.

Sensor Interfaces – Automotive Example

Automotive sensors are found in a broad range of demanding applications such as gas tank vapor and tire pressures; temperatures of various subsystems both outside and under the hood; and positioning of electromechanical devices for brake, steering and other systems. Many of these applications include a very tight set of requirements.

Many of these sensors employ a bridge architecture that produces a very small amplitude differential signal. These bridges exhibit random part-to-part variations, offsets and non-linearities, and these variations become more pronounced as chip process nodes shrink due, in part, to increasing process parameter variability with decreasing node feature sizes. System designers need to apply signal conditioning techniques to amplify and compensate for these variations so the output is an accurate linear signal for the system that interfaces with the sensor. Complicating the signal conditioning operation is the fact that automobiles present a severe operating environment for their electronic components. For example, sensor modules must tolerate large power supply disturbances and electrostatic discharge (ESD) spikes of several thousand volts, along with temperature ranges that can span -55°C to +150°C for under-the-hood components. This often requires sensor calibration in situ (i.e., when the sensor is connected to the complete sensor module, which necessitates field trimming of the control electronics).

As an example, Figure 1 shows the schematic for a programmable analog sensor signal conditioner from Texas Instruments (TI). The analog signal path amplifies the sensor signal and provides digital calibration for offset and gain. Calibration parameters are stored onboard in seven banks of OTP memory. Another TI signal conditioning chip, the PGA309, adds temperature compensation and stores calibration look-up values in external electrically erasable programmable read-only memory (EEPROM).

Figure 1. A Schematic for a Programmable Analog Sensor Signal Conditioner

TI’s PGA308 programmable analog sensor signal conditioner uses seven banks of OTP memory to
digitally calibrate amplifier offset and gain and to condition the bridge sensor’s output signal.

Typical sensor conditioning systems use Flash, EEPROM or electrical fuses (eFuses) to store coefficients to correct for sensor offset, range, temperature and non-linearity. These coefficients are determined and written during sensor module calibration. Data loss or corruption of this calibration and conditioning data during normal vehicle operation can lead to disastrous results in systems such as those used for braking or steering. Both Flash and EEPROMs exhibit reliability problems at high temperatures that can compromise the reliability of sensor modules that use these storage mechanisms, and vendors of these modules have to add additional circuitry to guarantee valid proper calibration data storage throughout the operating life of the module. An alternative solution is to use an embedded OTP memory that does not suffer the high-temperature reliability problems of Flash or EEPROM and provides a denser solution than an eFuse array.

A Foundry-Flexible Embedded OTP Memory Bit Cell

Analog IP core trimming and sensor conditioning techniques are well understood and have been successfully applied for several years using OTP memory to store trim coefficients. The difficulty is in identifying an OTP technology that simplifies process portability and scalability, is field-programmable, does not require process changes for standard CMOS implementation, and, for automotive and certain industrial applications, is reliable at high temperatures. Floating gate memory technologies (e.g., Flash), EEPROMs, ROMs and eFuses, all have shortcomings in one or more of the areas of cost, reliability, field programmability and retention at high temperature.

A good example of designing for process portability and scalability is the antifuse-based OTP split-channel, bit-cell architecture shown in Figure 2. The bit cell is based on variable oxide thicknesses – thick (input/output (I/O)) and thin (gate) – under a single transistor gate.

Figure 2. A One-Transistor, Split-Channel Bit Cell

The one-transistor, split-channel bit cell uses both I/O (thick) and core (thin) oxides under a single
transistor gate. The bit cell is programmed by an irreversible rupture of the thin oxide achieved by
applying a programming voltage to the gate.

The bit cell is programmed on the wafer, in a package or in the field by applying a high enough voltage on the transistor gate (the word line) to irreversibly breakdown the thin oxide. The programming voltage, ranging from 8.5V to around 5.5V for 130-nanometer to 65-nanometer processes, respectively, can be applied using an internal charge pump or from an external source. A programmed bit cell cannot be un-programmed under temperature or voltage stress.

Note that there are no lightly doped drain (LDD) or halo implants (used for leakage reduction) at the edges of the thin oxide. The implementation of “drain engineering” features such as these involves processing operations that are very foundry-specific. The breakdown region when a cell is programmed is confined to the channel below the thin oxide and exhibits very consistent characteristics from bit cell to bit cell within a memory array. This simplifies the task of porting OTP memory arrays based on the split-channel architecture from foundry to foundry, and also makes split channel-based OTP arrays more easily scalable to shrinking process nodes.

Split channel-based OTP macros can also be used in a differential read mode, which increases both the voltage and temperature operating ranges of macros (Figure 3). This is very useful for high-temperature operating environments such as those found in automotive applications.

Figure 3. A Differential Read Mode

A differential read mode (right figure) is available for split channel-based OTP arrays. Using two
physical bit cells for each addressable memory location eliminates the need for a read reference voltage
and increases the read margin, thus increasing both voltage and temperature operating ranges of the
memory array.

Table 1 shows a comparison between eFuse, ROM, embedded Flash and split channel-based memory for several desirable design characteristics. The table shows that a storage technology based on a split-channel, bit-cell architecture provides many of the benefits that analog and mixed-signal designers need to enhance the operation and yield of their IP cores.

Table 1. A Comparison between Traditional Memories

This table shows a comparison between traditional memories used to calibrate analog circuits and
condition sensor signals, and a memory array based on the split-channel architecture. If a ROM
redesign is needed, it will result in substantial mask and engineering costs.

Designing and implementing foundry-friendly IP just makes sense. Such IP allows an IP vendor to provide their products to a broader range of IP integrators and better serve their customers. IP integrators have enhanced flexibility to have their chips processed at multiple foundries and to take advantage of the reduced cost and higher integration capabilities associated with moving down the process node curve.

About the Author

Jim Lipman is currently director of marketing at memory IP provider Sidense. Prior to Sidense, Jim worked at Cain Communications as vice president of client services, TechOnLine as content director, and at EDN Magazine as application-specific IC (ASIC) and electronic design automation (EDA) editor. He also was employed by VLSI Technology, where he held various training, marketing and public relations positions, and did chip designs at both Hewlett-Packard and TI earlier in his career. Jim received his B.S.E.E. and M.S.E.E. degrees from Carnegie-Mellon University in Pittsburgh, Pennsylvania and his Ph.D. in electrical engineering from Southern Methodist University in Dallas, Texas. He also has a MBA from Golden Gate University in San Francisco, California. Jim is a senior member of the IEEE. You can reach Jim Lipman at 925-606-1370 or jim@sidense.com.

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