Parallel Testing Supplants Test Time as the New Cost-of-Test Measure

Anthony Lum, SOC Product Engineer, Advantest America Inc.

In the past, a typical wireless system was built primarily from a range of components and subcomponents. Common design practices of yesteryear featured functional blocks that were made up of transistors used for amplifiers. And mixers and discrete elements, such as matching circuits, filters and resonators, populated the system. As a result, the physical size of the early wireless systems and packaged subcomponents was comparatively bulky, cumbersome and less usable.

Wireless Consumer Product Evolution

The situation has continued to evolve rapidly. Around the mid-1990s, an integration of the functional blocks was realized, paving the way for the radio frequency (RF) system-on-chip (SOC). As RF SOC complexities increased along with higher levels of integration, wireless systems, such as cell phones and Wi-Fi, became more viable and ubiquitous in the home and workplace. However, as consumer demand increased, so did pricing pressures on SOC manufacturers. The market began to insist on lower cost product and delivery of a solution in smaller packages with more complexity. The challenges associated with providing more capable test solutions with lower cost-of-test are the subject of this article.

Figure 1. The Integration of a Discrete Component into a RF SOC

Many of the discrete components that formed a wireless application in the early 1990s are now integrated into RF SOCs.

Product Integration Creates Cost Pressures

The expanded capabilities of today’s RF devices map directly into longer test times. To address the need for lower costs, and the fact that test times are being reduced to a theoretical minimum, multi-device under test (DUT) solutions are required. Multi-DUT is an attempt to bridge the price-performance divide by testing a number of devices in parallel. In essence, multi-DUT aims to balance the physical limits of testing with the need to conserve capital resources and reduce cost-of-test with higher throughput. However, multi-DUT presents a number of other challenges in areas such as:

• RF instrument density.
• Loadboard layout.
• RF testing.
• Processing and packaging.
• Dimension and handler mechanics.

RF Instrument Density Challenges

RF test solutions have evolved in recent years. In the past, RF testers were typically “rack-and-stack” systems assembled from components to address a specific testing need. However, the test industry has moved to higher levels of integration, consolidating resources in the test head, rather than in a big rack of equipment.

Figure 2. The Evolution of RF Instruments

RF instruments have evolved into high-density, test head-resident monolithic modules.

Early RF systems from over a decade ago had only 12 ports built from several boxed stand-alone instruments. Today, by contrast, it seems that about every instrument of yesteryear has been integrated into a monolithic module. Density, which describes the number of instruments in a single module, has increased, thus allowing the assignment of dedicated RF resources to every device pin in a multi-DUT configuration. Today’s systems include a minimum of:

• 32 RF ports.
• Four vector signal generators (SGs).
• Four receivers.
• Four continuous wave (CW) stimuli.

Multiple instances of this capability can support up to 128 RF ports in a single test system. In the past, it would have required a room full of racks to provide this type of capability, but today, it is simply a few slots in the test head.

Of course, RF density is a plus from the standpoint of delivering many testing options in one package. However, automated test equipment (ATE) RF density alone does not solve the multi-DUT challenge. System vendors need to extend their solution beyond the boundaries of ATE resources.

Loadboard Layout Challenges

The next major DUT challenge is the layout of the loadboard. In fact, this may be the single biggest challenge in enabling effective multi-DUT. Historically, test resources have been provided in focused areas (RF resources in one corner, digital resources in another, mixed-signal resources in a third, etc.). Having a performance board environment that provides all necessary resources adjacent to all DUTs in a multi-DUT setup is very beneficial. Not only does this simplify the layout, but it also greatly improves measurement performance, resulting in faster test times and improved yield. For example, in a quad solution with four DUTs, it is preferable to have all required resources readily available and adjacent to each DUT to minimize coupling and achieve better isolation. As previously mentioned, having dedicated resources available to each DUT is critical. The alternative is adding switches or multiplexers on the loadboard and unnecessary complexity, which increases test time, reduces dynamic range and limits yield. Furthermore, test program generation and checkout will become much more complex.

Figure 3. A Variety of Socket Layouts for Multi-DUT Solutions

RF Testing Challenges

The very nature of RF testing is changing, which presents new challenges. The days of measuring traditional parametrics and trying to correlate electronic characteristics to ultimate system performance are waning. Issues such as gain, noise figure, third-order intercept point (TOI) and black box-scattering parameters are still important, but they are no longer the main focus. Today, what really matters is that the system-on-a-device actually performs as it is designed to perform. In the past, tests, such as gain and noise, were performed on RF devices, but now the focus is simply on whether the cell phone functions as intended.

For instance, if a consumer inserts a device into a cell phone, it is important that the cell phone doesn’t drop a call. Therefore, first and foremost, the functional aspects of a circuit, such as bit error rate (BER) and all other functional parameters, must be tested. So, in essence, testing has become more closely aligned with the end product.

As SOCs continue to evolve, there will be more functional tests and, necessarily, more emphasis among device makers on design-for-test (DFT) and built-in self-test (BIST).

Further complicating the test challenge, multiple in, multiple out (MIMO) techniques, which allow antennae to process many incoming and outgoing signals simultaneously with the development of true duplex-functional radio tests, need to be tested as if they were used in the end product (i.e., functionally).

At a minimum, functional tests include hybrid system-level tests such as:

• Adjacent channel power ratio (ACPR) (also known as adjacent channel leakage ratio (ACLR)): the ratio of transmitted power to power in the adjacent radio channel.
• BER.
• Error vector magnitude (EVM).

A visionary ATE solution needs to adapt to the continually shifting industry test paradigm, including DFT, BIST and, most importantly, full-functional system-level testing.

Processing and Packaging Challenges

When it comes to packaging, the great benefit of Moore’s Law is that more functionality can be integrated onto a single die. However, higher levels of integration also create other challenges. For instance, key system components can’t be isolated from one another. Therefore, if a transmitter is running at full output, the receiver “next door” must remain sensitive.

In response, engineers have developed solutions such as system-in-package (SiP): the combination of multiple chips in a single package. However, within these solutions, a variety of interconnective technology must be used to ensure functionality. However, this is by no means the end of testing challenges. For instance, pitch dimensions currently hovering around 0.4mm are getting smaller. With such a small space between contacts, the possibility of short circuits has never been greater. In addition, the reduced use of metals, such as lead, in packaging has led to what is sometimes called gumminess (i.e., packages are more soft, sticky and prone to poor electrical performance that needs be verified through tests).

Dimensional Challenges and Handler Mechanics

As previously noted, packaging has evolved significantly and continues to change. Generally, this translates into tremendous dimensional challenges. Early on there were small outline IC (SOIC) packages – large, plastic, rectangular, surface-mounted chip packages with gull-wing style pins. In addition to SOIC, package sizes are now being driven by a wide range of form factors and configurations in the market, including:

• Quad flat pack (QFP).
• Leadless chip carrier (LCC).
• Quad flat pack no lead (QFN).

Needless to say, some of these package types are particularly challenging for test. The big challenges include the limited space on performance boards and the ever-increasing drive for higher levels of test parallelism. For instance, LCC and QFN are great in terms of providing more options for electronic design solutions, but are much tougher for multi-DUT applications. Robotic handlers in high-volume applications involving LCC and QFN have difficulty meeting volume requirements. Also, while smaller packages take up less space on the loadboard, they also create a much bigger challenge in terms of signal routing. As signals converge, electrical isolation problems emerge.

Pick-and-place handlers are also facing difficulties, especially with regard to x-y axis pitch lengths and pin-one rotation. The open area on the guide plate is the fundamental limitation. Today, 1x4 and 2x2 quad-DUT configurations are used, but in the near future, 8x2 and 16x1 configurations will be needed. What is really needed is handlers that can space out parts more to help solve loadboard issues.

Reality-Testing, Multi-DUT RF Solutions

As previously discussed, in the past, packaging and testing challenges were considered from the vantage point of independent solution, each addressing a unique problem set without reference to the other. The industry can no longer afford to be myopic with regard to test challenges. The practical limits described here are real. Business as usual won’t work. The limits imposed by RF instrument density, loadboard layout, processing and packaging, RF testing, package dimensions and the mechanical capabilities of handlers must be recognized.

The new solution to efficient packaging and testing of RF products lies in a multi-DUT “test cell” approach. This will enable companies to address the complicated interrelationship of all elements in terms of a system and a testing solution, as it affords seamless communication and data flow between the ATE controller and modules.

To reiterate, multi-DUT solutions are only effective if they can execute efficiently with a high degree of parallelism. To accomplish this, the ATE system architecture must be streamlined for optimal data flow and communication to the instrument modules. In turn, high-density modules are needed with multiple source-and-capture resources to assure parallelism. The module resources must be distributed to accommodate optimal multi-DUT performance board layouts. Lastly, the performance board and system need to interface with a handler without incurring any electrical or mechanical performance penalties that would negate the multi-DUT solution’s parallel efficiency.

Only by this kind of thinking can the electronics industry meet the industry’s inevitable demands for higher quality and productivity.

About the Author

Anthony Lum joined Advantest in January 2006 as a SOC product engineer. He has over 20 years of RF/microwave industry test experience acquired at Texas Instruments and HP/Agilent. After acquiring his B.S.E.E. at Arizona State University in 1986, he joined TI where he developed microwave wafer and module test systems for military applications. He later moved into the semiconductor sector in 1990 and gained valuable experience in RFIC design/test and helped launch the RF/wireless business at TI. He joined HP/Agilent in 1996 as an applications engineer (AE) to help deploy and grow the installation of the HP84K RFIC tester to 250 units worldwide. He took an AE district manager position in 2000, where he successfully lead and developed a group of 93,000 AEs in the dynamic and challenging SOC market. He has authored and co-authored over 15 industry papers. Anthony Lum can be reached at a.lum@advantest.com.

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