Automating Analog IP Process Migration: The Next Frontier

K. T. Moore, Senior Director, Business Development, Custom Design Business Unit, Magma Design Automation

In the past, most of the semiconductor industry believed that the world had gone digital and deemphasized analog. As recently as last month, high-definition television – otherwise known as the digital television broadcasting system – replaced outmoded, traditional analog television systems with higher, better quality resolution.

And yet, analog is a hot topic these days. Late last year, for example, a keynote speaker at Electronica mentioned the advent of analog techniques to reduce the power of digital and help companies “go green.”

Today, most companies want to add analog functions to their digital designs. And therefore digital design is driving strong demand for advances in analog electronics.

This demand is driven, in large measure, by the need to integrate more functional blocks on a single IC or system-on-chip (SOC). To meet the functional and cost requirements within tight delivery schedules, designers must reuse significant portions of their designs and migrate them to smaller process technologies. Designer productivity must also increase.

Today, digital design reuse is common and used with great, measurable success. Intellectual property (IP) reuse methodologies are readily available and well honed for digital blocks because of the well-structured and cell-based design characteristics of the digital world.

Although design reuse methodologies across the board could be improved, analog IP reuse tools and methodologies are practically non-existent. An effective IP reuse methodology does not exist in the analog domain because analog design is far less standardized and far more irregular. Even when designers work with a well-defined standard, modifications may be needed. Development is difficult because analog and mixed-signal designs are susceptible to multiple design and process sensitivities. The varied tasks for analog chips present huge design challenges, and capturing an analog designer’s intent through automation has proven to be elusive as well.

While there have been several attempts to develop an analog-based reuse methodology, design teams ultimately rely on techniques that require many hours of brute-force simulation and plenty of manual effort. This lack of automation forces them to manually redesign the analog IP portion of the SOC each time it is migrated from one process technology to another.

Requirements for an effective reuse methodology include accelerating process migration because smaller process nodes allow for integration of more components and offer reduced fabrication costs. Unfortunately, many semiconductor companies cannot invest the time to retarget their analog IP and prolong their use of older process technologies. Analog designs and process technologies don’t easily transfer – think unpredictability and irregularity – limiting the size of the analog IP content that can be ported or optimized to a new foundry or technology. Maintaining accuracy, power, area or performance per the design specification has been difficult as well.

Another problem is that analog IP is too hard to reuse. It comes with all the integration issues associated with digital IP, in addition to a few unique analog challenges. Analog IP arrives as hard IP – GDSII layout blocks fixed in size and tied to a particular foundry and process – making it difficult to modify and integrate into the design.

In addition to technical challenges, the pressure to reduce turnaround time is significant. Producers of consumer electronic products (i.e., semiconductor companies) must introduce new products while capturing and maintaining market share in a competitive playing field. The ability to stave off competition depends on offering more product differentiation while at the same time improving margins and maintaining, if not increasing, the return on investment.

With more efficient analog IP design, reuse and migration methodologies, semiconductor companies could accelerate adoption of newer process technologies, and create and use more components from analog IP libraries. Such an approach would make it easier to differentiate their products while reducing manufacturing costs. Improved analog IP reuse is important for foundries as well. Not only would they benefit from greater use of advanced processes, but they would be able to build and license larger libraries of analog IP.

There is tremendous room for improvement in analog IP creation, migration, and reuse tools and methodologies. 2009 will see significant advances in this area. It is the next design frontier and one that will soon be conquered.

About the Author

K.T. Moore, a senior product director in Magma’s custom design business unit, is responsible for business development and marketing of Magma’s analog migration and simulation products. K.T. has more than 20 years experience in semiconductor design and electronic design automation (EDA). He has held various engineering positions with IBM and Texas Instruments. He started his EDA career with Valid Logic Systems Inc. and has held various sales and marketing positions with Cadence Design Systems, EPIC Design Technology and Synopsys. Moore received a B.S.E.E. and an applied physics degree from Case Western Reserve University in Cleveland, Ohio. You can reach K.T. Moore at kt@magma-da.com.

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