Design Challenges for Low-Power, Mixed-Signal CMOS SOCs

Dr. Vincent Peiris, Section Head, RF and Analog IC Design, Microelectronics, CSEM
Pierre-François Rüedi, Project Manager, Sensory Information Processing, Microelectronics, CSEM
Dr. Dragan Manic, Section Head, Industrialization and Production, Microelectronics, CSEM
Simon Gray, Head of Business Acquisition, Microelectronics, CSEM

The design of a system-on-chip (SOC) in deep-submicron CMOS is a challenging task for an IC designer because a variety of analog, digital, mixed-signal and radio frequency (RF) blocks must be embedded on a single die and function smoothly together. The design challenge gets even more complex when it comes to achieving ultra low-power capability for applications such as wireless sensor networks (WSNs), which translates into low-current consumption from supplies sometimes as low as 1V. For other applications such as machine vision, the challenge consists in packing a maximum amount of functionality within the SOC to benefit from miniaturization while achieving improved speed at low-power levels.

This article addresses some of the design challenges for such SOCs through three selected cases. First, an ultra low-power, 0.18-micron RF SOC targeting WSNs is presented. It includes a 2.5mA dual-band RF transceiver, a 50μA/MHz reduced instruction set computer (RISC) microprocessor, a sensor acquisition chain and a power management unit – all operating from a 1V supply. Second, a 0.18-micron SOC for low-power machine vision is highlighted, integrating an ultra-high dynamic range quarter video graphics array (QVGA) pixel array with a 50MHz 32-bit digital signal processor (DSP) and yielding a power consumption of 80mW. Third, an insight into the potential of microelectromechanical systems (MEMS) SOCs will be provided, focusing on next-generation, miniature and low-power 2.4GHz radio SOCs combining RF MEMS with CMOS.

An Ultra Low-Power 1V RF SOC

Many RF SOCs have been developed in the last decade, most supporting mobile phones and connectivity solutions such as Bluetooth or Wi-Fi. These SOCs draw fairly important currents (ranging from a few tens to a few hundreds of mA) from fairly high 2V to 3V supplies in such a way that the battery must be recharged every few hours or days.

In applications such as WSNs, ultra low-power consumption is mandatory to sustain applications that can run several years without changing or recharging their batteries. Because many nodes are deployed in a WSN, low cost is also a key issue, which implies using cheap alkaline batteries and designing an RF SOC that can be operated from supplies as low as 1V – the end-of-life voltage for such batteries.

An example of an ultra low-power, low-voltage (1V) RF SOC used in a WSN¹ and in a home automation application is illustrated in Figure 1.

Figure 1. An Ultra Low-Power, Low-Voltage (1V) RF SOC

An ultra low-power RF SOC in 0.18-micron is shown on the left and segmented to show the RF
section, the digital section including SRAM (DIG), the analog sensor interface (ANA) and the power
management unit (POW). On the right, a view of the WSN nodes built using the RF SOC.

The SOC in Figure 1 is integrated in a standard digital 0.18-micron CMOS process from TSMC. Its RF section features an ultra low-power, dual-band 433MHz/868MHz transceiver for short-range connectivity in industrial-scientific-medical/short-range-device (ISM/SRD) bands. The transceiver operates with 25kb/s frequency shift keying (FSK) or 2kb/s on-off-keyed (OOK) modulations. The SOC also embeds a sensor interface with a signal conditioner; a 10-bit, 10kHz analog-to-digital converter (ADC); and a 16-bit, sigma-delta, low-frequency ADC. The digital control unit is based on a low-power, 8-bit CoolRISC microcontroller with 22kB low-leakage SRAM. A power management block unit is also included to generate the necessary internal and external power supplies from the 1V to 1.5V battery voltage.

The main challenge for this RF SOC is to achieve low-power consumption for multi-year autonomy. For this purpose, the low-power requirements must be analyzed for all blocks of the SOC and at all levels.

• Radio Level: The RF SOC achieves 2.5mA in receive mode under 1V internal supply (hence with a very low 2.5mW power budget in active mode). With 1 percent duty cycling, which is affordable for a WSN, it is possible to reach around 25μA average current consumption, yielding roughly five years of autonomy from a single AA alkaline battery. To achieve this level, a thorough analysis of RF architectures is conducted and leads to the selection of a super-heterodyne scheme with a high intermediate frequency. This approach enables the reduction of power consumption in the critical high-frequency blocks such as the low-noise amplifier (LNA), the first down-conversion mixer and the voltage-controlled oscillator (VCO). In addition, even the high-frequency blocks are designed to operate in a weak inversion regime (also known as a sub-threshold regime and generally used for low-frequency analog blocks) whenever possible, clearly demonstrating that RF performance is achievable in 0.18-micron CMOS even with very low-current biasing conditions.
   
• SOC Level: In addition to the radio, all other parts of the circuit need to yield ultra low-power characteristics. In particular, the SOC is operated by a digital system whose static and dynamic power consumption must be in line with the global 25μA average target. A major issue is the non-negligible leakage current for large digital blocks in deep-submicron CMOS, which is proportional to the area. The digital section occupies a large part of the IC, which is mainly attributed to the 22kB of on-chip SRAM. To achieve below 3μA of static current (when the SOC is in sleep mode), a dedicated SRAM cell is designed and enables an order of magnitude savings on the leakage current thanks to an innovative bulk-biasing scheme. The processor’s dynamic current consumption, which is directly related to the clock frequency, is also an issue that is addressed with the design of a scalable-frequency CoolRISC processor. The latter can be clocked at 6.4MHz for operations needing speed and as low as 32kHz for low power. With this approach, power consumption in the digital part of the SOC scales with 50μA per MHz, which is significantly lower than for solutions using an external off-the-shelf microprocessor.
   
• CMOS Foundry Level: Designing a SOC in a standard CMOS process is mandatory to reduce wafer costs because no additional process options are used. On the other hand, there is the challenge of designing high-performance RF and analog blocks using baseline MOS and metallization features. For this RF SOC, a dedicated library of RF devices is developed and modeled, and uses only available metal layers for the inductors (no thick metal option), fringe capacitors and MOS device for the varicaps (no mixed-signal or RF options). In addition, clever analog design techniques taking into account the poor characteristics of the baseline CMOS process’ MOS devices are used to compensate for process tolerances. With this approach, the RF SOC could be successfully integrated in other foundries without RF and analog performance degradation, and the intellectual property (IP) is portable without change.

A Low-Power Vision SOC

Visual scene analysis involves processing large amounts of data. Furthermore, combining real-time capabilities with robust performance, even in environments with changing illumination conditions, is a challenging task. Key to fulfilling these challenges is achieving a high intra-scene dynamic range of the optical front-end and adequate data representation independent from the illumination level. The SOC approach offers the opportunity to closely develop the sensor, the processing means, tools and software to globally optimize the system, maximize robustness and processing speed, and minimize cost and power consumption.

The SOC illustrated in Figure 2 incorporates a 320x240 pixel array with a 32-bit icyflex² DSP/microcontroller, and is integrated in Tower Semiconductor’s 0.18-micron CMOS image sensor (CIS) process. It enables a single-chip vision system to perform image acquisition, analysis and decision making; however, a number of design challenges need to be overcome at the pixel and processor levels.

• Sensor Level: A high intra-scene dynamic range and adequate data representation is achieved at the expense of a more complex pixel design in comparison to standard image sensors. Each pixel incorporates a comparator and 10-bit memory to measure the time taken to integrate the local photo current over a fixed voltage range and store a digital code proportional to the logarithm of the duration. Packing photo-current integration nodes together with digital signals toggling during photo-current integration in a single pixel requires thorough analysis and minimization of parasitic couplings between nodes. The result is a 132dB intra-scene dynamic range logarithmically encoded on a 10-bit word with 149 steps per decade while achieving a fixed pattern noise of 0.51 least significant bits (LSB). This architecture lowers processing power requirements. First, the dynamic range is achieved without any adaptation to illumination changes. Second, the constant transfer function over the whole dynamic range means that the image processing is independent of the illumination level. Third, the logarithmic encoding enables the computation of a contrast representation (i.e., the relative illumination change between neighboring pixels) by simple subtractions. As contrast is independent of the illumination level, it enables the stable representation of the visual field even in uncontrolled illumination conditions.
   
• Processing Level: The icyflex processor³ is optimized for low-voltage (1V), low-power applications; therefore, to satisfy the requirements associated with image processing, it is necessary to act at several levels. First, the digital supply voltage is raised to 1.8V, and the processor is optimized to achieve a 50MHz clock frequency. Second, contrast computation is performed on the fly, on eight pixels in parallel, and during the transfer of data from the pixel array to the processor’s memory. Third, the icyflex processor’s data processing unit is complemented by a graphical processing unit (GPU) tailored for vision algorithms able to perform simple arithmetic operations on 8- or 16-bit data grouped in a 64-bit word. Fourth, vision applications’ memory requirements are difficult to satisfy with on-chip memory alone. Therefore, in addition to an on-chip 128KB SRAM used as program and data memory, a 100MHz SDRAM interface is implemented. To maximize flexibility of use and connectivity, different communication interfaces are also implemented.

Figure 2. A Low-Power Vision SOC

A low-power vision SOC in a 0.18-micron process is shown on the left. On the right,
a miniaturized low-power machine vision camera embedding the vision SOC.

From RF SOCs to RF MEMS SOCs

The SOCs described in the previous sections embed a wide set of functions (i.e., RF, microcontroller, SRAM, DSP, analog sensor interface, vision sensor, power management unit, etc.) on a single CMOS chip, enabling interesting miniaturization levels for the targeted applications.

For wireless applications where extreme miniaturization is required in addition to low-power consumption, such as for implanted medical devices or hearing instruments, innovative approaches need to be investigated beyond CMOS SOC integration. The combination of RF MEMS technologies, such as RF bulk acoustic wave (BAW) resonators and filters, with CMOS technologies provides excellent perspectives for realizing MEMS-based RF SOC solutions⁴ fitting within a few mm³ instead of a few cm³.

Figure 3. A Next-Generation, Ultra-Miniature Radio Platform

On the left, a 2.4GHz RF IC assembled with a BAW RF MEMS filter chip is shown.
On the right, a silicon resonator MEMS co-assembled with a CMOS timing IC.

Figure 3 shows a next-generation, ultra-miniature radio platform where a BAW MEMS chip is co-assembled with a 2.4GHz RF CMOS IC. Whereas traditional integrated radio solutions rely on bulky external components (e.g., RF SAW filter, RF matching devices and low-frequency crystals), the MEMS and CMOS SOC strategy shrinks these functions by using the miniature BAW RF MEMS and the silicon resonator MEMS counterparts to achieve an order of magnitude reduction in the volume of the radio solution as a result of co-assembling the MEMS and the CMOS SOC by flip-chip or wafer-scale assembly.

Compared with the purely CMOS RF SOC previously discussed, the heterogeneous co-assembly of the RF CMOS functions together with the MEMS devices presents additional design challenges.

• At the system level, the interaction between MEMS and CMOS calls for novel architectures and signal processing algorithms to accommodate the imperfections and limitations of the MEMS devices.
   
• At the assembly level, dedicated wafer-level packaging or system-in-package (SiP) technology platforms need to be developed to co-assemble the MEMS devices with the CMOS SOC. The subsequent connectivity-related constraints also need to be accounted for when designing the MEMS and the circuits, especially when a variety of MEMS are included (e.g., BAW MEMS; silicon-based, low-frequency resonators; and RF switches).

Conclusion

This article described a selection of innovative, low-power SOCs, ranging from pure CMOS SOCs to heterogeneous SOCs combining CMOS and MEMS. The design of such miniature and highly integrated circuits and systems offers a variety of design challenges and innovation fields. In the context of low-power consumption, the SOC examples presented highlight the importance of multi-disciplinary approaches when designing and combining analog, digital, vision, RF and even MEMS within a single miniaturized SOC.

About the Authors

Vincent Peiris received his M.S. and Ph.D. degrees in electrical engineering from the Swiss Federal Institute of Technology (EPFL), Switzerland in 1989 and 1994, respectively. In 1995, he was a visiting scientist at the Microsystems Technology Laboratory of MIT, USA. From 1996 to 1999, he was with LeCroy Inc, Switzerland. In 1999, he joined the Swiss Center for Electronics and Microtechnology Inc. (CSEM), Neuchâtel, Switzerland, where he has been active in the field of RF CMOS IC design. Since 2002, he has led the RF and analog IC design group of CSEM.

Pierre-François Rüedi received his M.S. degree in microtechnology from EPFL, Lausanne, Switzerland in 1990. From 1990 to 1992, he worked for Seiko Instruments, Matsudo, Japan, where he was involved in the design and characterization of SRAM memories. He has been with CSEM since 1992 and is presently a project manager in its microelectronics division, working in the domain of analog and mixed-mode design of optical sensors.

Dragan Manic has been with CSEM since 2007 and is presently the head of industrialization and production within its microelectronics division. Prior to joining CSEM, Dragan served as product engineering, technology and reliability specialist at Semtech and Xemics. Dragan received his M.S. degree in electrical engineering from the University of Nis, Serbia in 1994 and his Ph.D. degree in microtechnology from EPFL, Lausanne, Switzerland in 2000.

Simon Gray is responsible for business development in CSEM’s microelectronics division. Simon has more than 20 years experience in the semiconductor industry, including engineering and marketing positions at Philips, BP, Xemics and Semtech. He has a B.S. degree from Nottingham University and an MBA from The Open University.

For additional information on the presented subject, you can contact Simon Gray at simon.gray@csem.ch or +41327205080.

Acknowledgments

The authors wish to acknowledge the contributions of CSEM’s design teams within its microelectronics division for the three SOC examples presented in this article. For the RF SOC¹ , the authors would like to acknowledge the support from Hager Research and Semtech, as well as their contributions to the design of the SOC and its industrialization.

Resources

¹V. Peiris, et. al., “WiseNET, An Ultra Low-Power RF Transceiver SoC and Communication Protocol Solution for Wireless Sensor Networks,” Advances in Analog Circuit Design (AACD) 2006 – High-Speed A-D Converters, Automotive Electronics and Ultralow Power Wireless, 345– 376, Edition Springer, Berlin, Germany (2006).
²P.-F. Rüedi, et. al., “An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications,” ISSCC Dig. Tech. Papers, pp. 15-16, Feb. 2009.
³C. Arm, et. al., “Low-Power 32-Bit Dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU Core,” ESSCIRC Dig. Tech. Papers, pp. 190-193, Edinburgh, Sept. 2008.
⁴David Ruffieux, et. al., “2.4 GHz MEMS-Based Transceiver”, ISSCC 2008, San-Francisco, paper 29.1, pp. 522-523.

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