American Semiconductor released its FleX™
extreme wafer thinning process. The unique FleX
wafer thinning process is capable of completely
removing the handle silicon of a silicon-on-insulator
(SOI) wafer, yielding fully functional,
flexible wafers with a final silicon thickness of
<2000 angstroms. As an additional benefit, FleX
allows post-thinning fab processing.
American Semiconductor is a U.S. foundry
offering pure-play, on-shore foundry services,
including custom fabrication for copy smart or copy
exact replication and Flexfet™ advanced CMOS
technology. Flexfet is a unique, independent
double-gated transistor technology that provides
ultra low-power, dynamic threshold control and
inherent radiation tolerance.
For additional information, contact:
Rich Chaney
(T) 208-336-2773
(E) richchaney@americansemi.com
(W) www.americansemi.com
austriamicrosystems’ business unit Full Service
Foundry expanded its cost-efficient and speedy
application-specific IC (ASIC) prototyping service,
multi-project wafer (MPW) or shuttle run, in 2009
with a more extensive schedule.
As part of the commitment to provide best-in-class analog semiconductor process technology,
manufacturing and services, austriamicrosystems
now offers three prototyping runs for its advanced
0.18μm high-voltage CMOS technology H18,
a joint development with IBM. In addition, four
MPW runs for foundry customers are available in
the CMOS7RF base technology. The leading-edge
0.35μm CMOS, high-voltage CMOS, high-voltage
CMOS with embedded Flash and SiGe BiCMOS
technologies complete the industry-recognized
MPW service.
The service, which combines several designs
from different customers onto one wafer, offers
significant cost advantages for foundry customers,
as the costs for wafer and masks are shared among
a number of different shuttle participants. The full
schedule, including detailed start dates per process,
is available on austriamicrosystems’ Website.
For additional information, contact:
Ron Vogel
(T) 408-345-1790
(E) ronald.vogel@austriamicrosystems.com
(W) www.austriamicrosystems.com
Chartered Semiconductor Manufacturing
and A*STAR’s Institute of Microelectronics
(IME), Singapore successfully optimized a
range of fine-pitch packaging technologies for
copper metallization and low-k dielectric silicon
processes at 65nm and below. The Chartered-IME
collaboration has led to a greater understanding of
chip-package interaction for low-k devices through
modeling, simulations and reliability verifications
on silicon. The collaboration’s results provide
package designers with benefits from silicon-proven
solutions and modeling tools to characterize the
impact of fine-pitch package on silicon early in the
design development cycle, which should improve
manufacturability and back-end-of-the-line yield
performance.
For additional information, contact:
Tiffany Sparks
(T) 408-941-1185
(E) tiffanys@charteredsemi.com
(W) www.charteredsemi.com
Pioneering the open foundry business model
in China since 1997, CSMC Technologies is
a leading pure-play specialty analog foundry
providing fabless design houses and integrated
device manufacturers (IDMs) with 6-inch and
8-inch manufacturing services. CSMC’s Fab 2
commences 8-inch wafer production in 2008 with
emphasis on high-voltage analog, mixed-signal
and power processes. The target capacity of Fab 2
is 30,000 8-inch wafers per month by the end of
2009, with process technologies advancing to the
0.13μm node.
For additional information, contact:
Jessie Shen
(T) 86-510-88113349
(E) shenj@csmc.com.cn
(W) www.csmc.com.cn
IBM Microelectronics added the semiconductor
industry’s first 45nm SOI foundry offering and its
accompanying design kit to its portfolio. 45nm is
IBM’s sixth generation of SOI technology and is a
key driver in many collaborative designs with clients
– including networking, storage, gaming and other
consumer applications. IBM testing has shown the
potential for 45nm SOI to offer up to 30 percent
performance improvement or 40 percent power
reduction when compared to the industry-standard
bulk CMOS technology. The new IBM 45nm
SOI foundry offering is now available to original
equipment manufacturing (OEM) customers to
take advantage of this cutting-edge technology.
For additional information, contact:
Jennifer Chu
(T) 802-769-6616
(E) jwchu@us.ibm.com
(W) www.ibm.com
Jazz Semiconductor, a Tower Group Company,
announced a series of worldwide technology and
marketing conferences with Tower Semiconductor
to present analog-intensive, mixed-signal (AIMS)
technologies and design enablement capabilities for
the production of advanced ICs. The conferences
target cross-selling opportunities among the diverse
customer bases of both companies.
Jazz also announced that Ubidyne selected
its 0.18μm SiGe BiCMOS process to develop
the world’s first pure digital radio system to
enable mobile infrastructure equipment vendors
worldwide to significantly improve performance,
flexibility and coverage.
In addition, Jazz announced that Fujitsu
Microelectronics Limited has licensed its high-precision
radio frequency (RF) models and design
kits to create a time-to-market advantage for
90nm and 65nm RF CMOS customers.
For additional information, contact:
Melinda Jarrell
(T) 949-435-8181
(E) melinda.jarrell@jazzsemi.com
(W) www.jazzsemi.com
MagnaChip Semiconductor, a leading Asia-based
designer and manufacturer of analog and
mixed-signal semiconductor products for high-volume
consumer applications, announced the
availability of its industry-leading 0.18μm and
0.35μm advanced bipolar CMOS DMOS (aBCD)
process technologies for foundry customers.
MagnaChip’s aBCD process technologies
represent the latest solutions of application-specific
technology to meet the specialized customer needs
for specific applications. The 0.18μm aBCD
process is suitable for complex, highly integrated
power management ICs such as those found in
mobile handsets. The 0.35μm aBCD, with higher
voltage and power capabilities, is well suited for
applications such as light-emitting diode (LED)
driver ICs for liquid crystal display (LCD) TVs
and notebooks.
For additional information, contact:
Andy Brown
(E) andy.brown@magnachip.com
(W) www.magnachip.com
MOSIS announced support for the IBM 45nm
SOI CMOS (12S0) process. The design kit
and ARM standard cell library is available now.
Access is already available via MOSIS for a
variety of other IBM (CMOS, RF CMOS, SiGe
BiCMOS), TSMC (CMOS and RF CMOS),
ON/AMI (CMOS and HV CMOS) and
austriamicrosystems (CMOS and HV CMOS)
processes. All technologies are available for
prototyping (e.g., 40 pieces), mid-range (e.g.,
500, 2000 pieces) and small-volume production
quantities (i.e., dedicated runs which can start at
any time). Frequent multi-project runs provide
convenient access to designers and facilitate
quick application development. For additional
information, including the MOSIS fabrication
schedule, price list, design flows, intellectual
property (IP) and further technical details, please
visit MOSIS’ Website.
For additional information, contact:
Wes Hansford
(T) 310-448-9400
(E) support@mosis.com
(W) www.mosis.com
To offer value to its global customers, SilTerra
Malaysia released the foundry-compatible 110nm
CMOS logic technology as the cost reduction path
for 130nm CMOS logic design. This technology
offers the ideal combination of speed, power and
density to the PC connectivity, communication and
consumer markets. The 110nm technology applies
10 percent linear optical shrink on customers’
130nm graphic design system (GDS) database
and mask-out with tighter pitch to generate more
die per wafer. In addition, the 110nm technology
is optimized to ensure silicon models and electrical
target are matched to 130nm specification. The
technology is currently in pilot production with
foundry design kits supported.
For additional information, contact:
Koh Meng Kong
(E) mengkong_koh@silterra.com
(W) www.silterra.com
SVTC Technologies partnered with Entrepix to
provide 300mm chemical mechanical polishing
(CMP) development and production services for
customers who use the Tool Access Program (TAP)
at the SVTC fab in Austin, Texas. CMP is a critical
process step in semiconductor manufacturing. The
partnership allows each company to leverage their
individual strengths, with SVTC furnishing a state-of-the-art manufacturing environment with a full
suite of process and metrology tools, and Entrepix
providing CMP engineering and operations
experience. Under the terms of the agreement,
all CMP processing, technology support and
customer interface for SVTC’s 300mm TAP will
be performed by Entrepix’s engineering team at
SVTC, following the same outsourcing model
Entrepix uses at its foundry in Tempe, Arizona.
SVTC’s TAP provides manufacturers with access
to more than 200 tools covering such processes
as lithography, etch, CMP, cleaning, coating
and metrology.
For additional information, contact:
Ashwin Kumar
(T) 512-356-2312
(E) ashwin.kumar@atdf.com
(W) www.svtc.com
Taiwan Semiconductor Manufacturing
Company (TSMC) announced plans to deliver
its 28nm process as a full-node technology. This
process offers the option of both high-k metal gate
(HKMG) and silicon oxynitride (SiON) material
to support different customer applications and
performance requirements. Initial production is
expected during Q1 2010.
TSMC also announced volume production of
the foundry segment’s only 40nm semiconductor
manufacturing process with the successful ramp
of its 40nm general-purpose (G) and low-power
(LP) versions. The 40nm process is one
of the semiconductor industry’s most advanced
manufacturing process technologies. The 40LP
process targets low-power applications, including
cellular baseband, application processors, portable
consumer and wireless connectivity devices.
For additional information, contact:
Wendy Matthews
(T) 408-382-8030
(E) wmatthews@tsmc.com
(W) www.tsmc.com
The Foundry Company’s highly differentiated
Automated Precision Manufacturing (APM)
enables a level of synchronization and automation
that is unmatched in the industry. APM is
currently employed in its Dresden fabs (and will
also be used in its forthcoming New York facility)
to act as a central nervous system, using more
than 400 patented technologies to provide tight
integration and analysis to ensure maximum
efficiency. As wafers enter and exit processing,
APM’s sophisticated infrastructure constantly
monitors The Foundry Company’s customers’
products by collecting and analyzing information
from the toolsets. Using real-time analysis of
this data, APM modifies the processing recipe to
ensure that the resulting products have minimal
defects and maximum quality.
For additional information, contact:
Jon Carvill
(E) jon.carvill@amd.com
(W) www.newglobalfoundry.com
Tower Semiconductor earned the Platinum
Award for the third year in a row from the Standards
Institute of Israel for quality, automotive, safety,
information security and environment systems.
Also, Tower was ranked by Deloitte Israel as one
of the 2008 Technology Fast 50 for the second
year in a row based on five-year revenue growth.
In addition, Yitran Communications and Tower
announced the production launch of Yitran’s
IT700 PLC module, a small-sized, highly robust,
low-cost solution suited for an infinite number of
command and control applications.
For additional information, contact:
Melinda Jarrell
(T) 949-435-8181
(E) melinda.jarrell@tower-usa.com
(W) www.towersemi.com
UMC has released its Silicon Shuttle multi-project
test wafer program schedule for 2009. The Silicon
Shuttle program provides a cost-effective means
for customers to verify their designs, prototypes
and IP in UMC silicon. The program allows
separate “seats” to be purchased on the same
Silicon Shuttle test wafer, allowing customers to
split the overall mask cost among multiple parties
to reduce the cost per customer to a fraction
of the total. The 2009 schedule features several
shuttle runs for UMC’s leading-edge 45/40nm
technology, as well as monthly 65nm launches
(subject to demand). Please visit UMC’s Website
to view the full schedule.
For additional information, contact:
Richard Yu
(T) 886-2-2700-6999 ext. 6951
(E) richard_yu@umc.com
(W) www.umc.com
