Q: S3’s primary end market is consumer, which brings great success, but also tight market windows. Therefore, it is important to deliver first-time-right intellectual property (IP). To reduce risk, mixed-signal IP must be proven in silicon. However, while silicon-proven IP is good, integration still remains an issue. How can IP vendors ensure stable IP integration (e.g., early access to stable process data from foundries)?

A: To receive accurate information from your foundry partners, it is very important to create close relationships with them. However, when it comes to integrating mixed-signal IP, especially high-performance IP, such as the IP developed at S3, an IP vendor that has extensive experience in integrating such IP into large systems-on-chip (SOCs), which are often dominated by noisy digital circuitry, brings a clear advantage to its customers. As an IP vendor, you must actively support the customer by advising them on how to avoid issues through proper guard rings and routing. At S3, we do this by providing detailed integration guidelines, offering support during integration and encouraging our customers to involve us in reviewing their final Graphic Design System II (GDSII) so we can identify any potential issues that might impact the performance of our IP as it is embedded in their design.

A major advantage for S3 has been the 20 plus years of IC design service experience that we have accumulated. Most of this experience has come from SOC projects where we have had the responsibility of integrating various third-party IP and ensuring performance issues are avoided.

Q: As consumer demand for devices continues to grow, companies must start new product developments quickly, which means mixed-signal IP will continue to be increasingly sourced externally. So obviously a need for more high-quality analog/mixed-signal third-party IP exists. What standards or processes does S3 currently have in place to guarantee they deliver high-quality IP to their customers?

A: We have worked with various foundries that have programs in place for qualifying third-party IP, which aid the industry in improving quality. Before these foundries promote any IP, they want to see it qualified, which includes consideration of it being in production. In addition, GSA has developed the comprehensive Hard IP Quality Risk Assessment Tool, which enables companies to collect important information about an IP vendor, its design methodology and the IP under evaluation to enable risk assessment. From an IP development perspective, we have very well-defined project management and engineering processes, which come from many years of analog/mixed-signal and other IC design projects. These projects have often been multi-site, and to successfully execute such complex projects, we have developed rigorous processes as identified by our longstanding quality accreditations such as ISO 9001.

Q: The fundamental problem GSA has noted in the analog/mixed-signal space is that customers are looking to a key point of responsibility to develop and strengthen linkages in the supply chain. Customers are looking for someone to address issues such as a lack of accurate models, managing the power budget, over customization, choosing the right process and increasing the planning through the entire process, including the consideration of packaging very early on. However, it seems neither the foundries nor the IP or EDA industries are willing to bear this responsibility. In your opinion, where do most of these issues exist and whose responsibility is it to see these issues resolved?

A: At older geometries, the issues described pose less of a problem, as the processes, models and tools are mature. Most of these issues arise when dealing with new geometries. The industry should encourage non-technical customers to take advantage these new geometries. One response to this has been the rise of fabless application-specific IC (ASIC) companies that can identify technical issues and risks around using less mature geometries and help customers make decisions on the level of risk they are willing to take, and the fabless ASIC organizations manage accordingly.

Clearly, each party has its own responsibilities (e.g., the foundry is responsible for accurate process models, while the SOC team is responsible for power budgets). The IP vendor is responsible for ensuring that the specifications it promotes in its datasheets are accurate and reflect what the performance will be in silicon. The key issue here is the need for silicon-proven mixed-signal circuits, such as high-performance analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and phase-locked loops (PLLs), at least at the geometry in question. However, when the customer demands customization, the link to this silicon-proven model breaks. The SOC architect must realize that to constrain costs and risks, greater effort must be put forth to use off-the-shelf IP solutions.

Q: On the other hand, despite the challenges that exist in this fledgling infrastructure, there are a number of emerging growth companies focused on analog design services and EDA tools that many in the industry appear to be unaware of. With start-ups traditionally being a valuable source of innovation, how can the industry strengthen their support for these companies and bring them to the forefront during the economic downturn?

A: In today’s tough economic climate, it is vital for organizations to outsource what they can and focus their internal resources on core competencies. Start-up companies providing analog design services and EDA tools can help chip companies, both fabless companies and integrated device manufacturers (IDMs), make the best use of their assets.

A critical challenge facing small start-ups is limited access to funding, which is threatening their future. To ensure start-ups have efficient funds, there has been a flow of funding from large original equipment manufacturers (OEMs) and semiconductor companies to the supply chain. Most of these large companies are funding non-recurring engineering (NRE) efforts, paying for the development of IP they need. These large companies understand that this funding helps build a sustainable supply chain and gives them access to innovation. Without aid from these large companies, start-ups must source funds externally, which may not be presently available, and if they are, are only available at a high-risk premium.

Q: As mentioned previously, over-customization has long been a technical challenge in the analog/mixed-signal design infrastructure. There continues to be a lack of standard electronic, voltage, power, quality and verification specifications, as well as system partitioning models. Are there areas where standards could be developed to aid the market development for analog/mixed-signal devices that would address some of these areas? If so, where do you see the initiative forming to take responsibility for these standards?

A: S3 primarily delivers high-performance ADCs, DACs, PLLs and analog front-ends (AFEs). There are a number of key parameters (e.g., signal-to-noise ratio (SNR), signal-to-noise and distortion (SINAD) and spurious-free dynamic range (SFDR)) that are generally used to specify this IP. There can be elements of specmanship that make it difficult for the purchaser to compare apples with apples. GSA can reduce this difficulty by setting guidelines to assure users of mixed-signal IP that what they are licensing is indeed what they need.

Effective customer education is needed. IP customers are often applying considerable pressure to have variants of what an IP vendor is offering. This is often driven by technical requirements, and the cost and risk associated with these requirements is not fully appreciated. During the current economic downturn, customers will be more interested in the cost- and risk-reduction benefits of buying off-the-shelf IP rather than customization. And those customers who don’t make this shift run the risk of becoming a casualty of the downturn.

Q: In July 2008, GSA released its Analog/Mixed-Signal/Radio Frequency (AMS/RF) Process Checklist to specifically address the topic of selecting an appropriate process and process options for a specific design application. While the Checklist is beneficial to semiconductor companies in choosing the right process, going even further, do you believe the industry will be able to streamline a few common processes despite the analog/mixed-signal nature of unique process design?

A: Economic pressure will force the industry towards a convergence of processes. An element of this has already happened with the convergence in the fab sector, where groups of major semiconductor companies and fabs have aligned their processes. On the other hand, there is pressure to differentiate and add value. To have a viable, vibrant industry, there must be balance.

Q: The design loop for analog/mixed-signal is often six to eight times, and often, the schematic must be re-architected to go into an optimization process. What advice can you provide to companies to manage or even decrease these loop backs?

A: At S3, we own an optimization tool that is used for front-end design, allowing us to very quickly get to the schematic stage. In one design loop, this optimization engine ensures that the architecture chosen and combined with the technology process in question will lead to a silicon implementation that meets the stated specifications. In addition to the tool, a company must have experienced engineers who know the architectures and have deep sub-micron (DSM) experience at leading-edge geometries. Also, a company must enact a rigorous review process that is based on years of analog/mixed-signal design. To compete, a company must have significant experience in analog/mixed-signal design. If they do not have the necessary experience, they are better off simply licensing-in the analog/mixed-signal design in the form of IP from an analog/mixed-signal IP vendor.

Q: Analog/mixed-signal design needs more EDA support; however, the EDA industry is suffering. While the semiconductor industry largely depends on the EDA industry, there is little investment from semiconductor companies into EDA. From the perspective of an IP company, how crucial is it that the EDA industry continues to innovate?

A: We absolutely need innovation from the EDA sector, particularly in the area of analog/mixed-signal design. Compared to digital design, analog/mixed-signal design tools have not brought the same productivity gains. However, with analog/mixed-signal circuits now occupying such a significant portion of a typical SOC, there will be increased efforts in this area. While S3 has its own optimization tool, it is not our core business, and our preference would be to find suitable tools from EDA vendors. With the various recent tool developments, such as M-Design from Mephisto Design Automation (MDA) and the custom productivity enhancement and quality standardization tool from IC Mask Design, we do see progress being made. One common benefit of these innovative, new tools is that they provide productivity enhancements through semi-automation.

Q: It is widely known that business success is largely driven by creativity and differentiation. From your standpoint, what factors need to be considered in establishing creativity to enhance IC performance and yield, specifically in the analog realm?

A: Four important points need to be addressed here. First, a company must acknowledge that creativity adds value. Secondly, it needs to decide what creativity it desires to keep for itself. Thirdly, after reaching this decision, a company should feel confident that they can attract, retain and reap the rewards from this creativity. Finally, a company must recognize that there will be times when they will be unable to confine the world’s best creativity in-house. However, it is better to have access to the world’s best, than have a sub-standard team in-house. This is not so much outsourcing, but rather licensing-in the best talent.

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