Emulation Becomes Secret Weapon for Designers of Consumer Electronics

Lauro Rizzatti, General Manager, EVE-USA

As the global economy slows to a crawl, semiconductor companies zealously search for new business opportunities in the consumer electronics industry while balancing the challenges of this demanding marketplace.

To answer the challenge, chip designers who are intent on finding new applications for consumer electronics devices have looked to hardware emulation, a verification tool with a long history. These designers advocate adding this popular solution into the verification strategy to produce a higher quality consumer electronics device in less time and more cost effectively.

In fact, emulation is employed worldwide as a secret weapon for fighting the verification battle, but this is a fairly recent phenomenon. The embracement of emulation has evolved rather slowly over the past 20 years. It was first adopted by central processing unit (CPU) and graphics chip companies in the 1990s driven by the raw complexities of their designs. Emulation spread into the wireless community in the early 2000s due to the extensive use of embedded software in their designs. And today, it is widely accepted by the entire spectrum of consumer electronics products companies, from digital TV to set-top boxes, digital still cameras and camcorders, multi-function printers and more.

Hardware design is a difficult discipline, and the emergence of system-on-chip (SOC) design has made it even more so. In fact, finding a bug in a SOC is like finding a needle not in one, but in two haystacks: a hardware haystack and a software haystack. Too often, the software team claims it is a hardware bug, while the hardware team snaps back at the software team that it is a software bug.

Emulation can be invaluable for debugging hardware and for testing the integration of hardware and software within SOCs well ahead of first silicon. When hardware designers and software developers, two disparate parts of the engineering team, use emulation, they’re able to share the same system and design representations. Thanks to combined software and hardware views of the design, they are able to work together to debug hardware and software interactions. However, not all emulation systems provide the acceptable speed of execution to process billions of verification cycles in a short period of time as required in embedded designs.

Emulation allows engineering teams to plan more strategically and to implement a debugging approach based on multiple abstraction levels, not to delve into the two haystacks independently from one another. Teams can track a design problem across the boundary between the embedded software and the underlying hardware to determine whether the problem lies in the software or in the hardware.

A debugging methodology based on multiple abstraction levels starts with embedded software at the highest level and moves down in abstraction all the way to trace the behavior of individual hardware elements. Starting from a database comprised of multi-billion clock cycles, a software debugger can localize a problem to within a few million clock cycles. At this level, either the software team quickly identifies the source of each problem in the software code or they call in the hardware team which uses a software-aware hardware debugging approach to zoom in to a lower level of abstraction.

At this stage, the methodology calls for monitors, checkers and assertions implemented through hardware transactors, which avoid speed degradation and help narrow down the problem to a few thousand cycles. Once the collected data at those two levels has been reviewed, emulation allows them to move down to the signal level. They can analyze the information via register transfer-level (RTL) waveforms of the identified period of time and trace its likely origin. At this stage, either a hardware bug is unearthed or the hardware is absolved from failure. In the latter case, it forces a decision to move back to the software environment.

Navigating between different abstraction levels—from software through hardware and backward—avoids long simulation runs and massive amounts of detailed data (Figure 1).

Figure 1. Emulation Provides an Ecosystem for Software and Hardware
Debugging, Monitoring and Checking Capabilities, and Hardware Waveforms

The multi-level debugging methodology would not be possible with software simulators because they are too slow to effectively execute embedded software. Indeed, they would run for weeks, if not months, to process billions of cycles on designs whose sizes reach into several tens of millions of application-specific IC (ASIC)-equivalent gates. This is an unacceptable time constraint for producers of consumer electronics devices.

Just as emulation is forcing simulation to take a back seat, new emulation systems are replacing traditional “big box” versions because they run faster, are easier to use and are considerably less expensive.  And they are environmentally friendly since they consume a fraction of the power dissipated by the bigger versions, require significantly less space and weigh a small percentage of the massive traditional boxes. For all these reasons, emulators were not popular until now (Figure 2).

Figure 2. Comparison of Four Verfication Tools Based on Three Criteria

Price, of course, is a main consideration. EVE surveyed close to 800 attendees at EDSFair 2009 in January in Japan and found that price is the most important consideration when choosing an emulator.  Emulation has evolved from the early days of emulators based on standard field-programmable gate arrays (FPGAs) to custom emulators and back again to emulators based on FPGAs. One reason for the “return to the origins” is economical. Retooling and non-recurring engineering (NRE) charges are exceedingly expensive below 65-nanometer. An emulation market of $200 million is not big enough for a large electronic design automation (EDA) vendor to justify at least $30 million to develop a custom chip.

On the other hand, there is a clear and sensible roadmap through the use of standard FPGAs at 45- and 32-nanometer and beyond. But there are two more reasons for the inversion of this trend and the re-adoption of standard FPGAs: capacity and performance. In 2008, the largest commercial FPGAs could implement about two and a half million ASIC-equivalent gates. In 2010, the number will jump to five million ASIC gates and to eight million gates in 2011. The capacity of standard FPGAs will continue to double every two years while pricing drops by a factor of two.

Likewise, the increase in performance will follow the same curve. In fact, in 2012, it will be possible to produce a 100-million ASIC gate emulator with 16 FPGAs for less than $50,000. This machine will execute at approximately 10MHz.

Conversely, at 65-nanometer, the manufacturing cost of a 100-million ASIC gate custom emulator will be in the neighborhood of $500,000 and will run at 500kHz. High costs and limited speeds are making this type of emulator uncompetitive and inadequate for software developers who require a bare minimum speed for 1MHz, but would appreciate speeds of several megahertz.

Moreover, design teams are opting out of using the in-circuit emulation (ICE) mode, a style of emulation popularized in the 1990s. The alternative to ICE is transaction-based verification. Conceptually, the idea is simple. Tests are written at high levels of abstraction, and the conversion from high-level commands to bit-level signals is moved into a dedicated entity called a transactor. By mapping the transactor onto an emulator, acceleration of five or six orders of magnitude, compared with simulation-based verification, can be easily achieved. Transactors permit to build a virtual test environment in place of a physical test bed as done via the ICE approach by replacing a set of speed bridges (Ethernet, Peripheral Component Interconnect (PCI) or Universal Serial Bus (USB)) with an equivalent set of transactors (Figure 3).

Figure 3. Emulation Using a Virtual Test Environment Based on
Transactors in a Wireless Application

In general, an ICE test bed serves one specific design and isn’t reusable on another, while transactors can be reused on any design. In the ICE approach, designers must bear with the quirks of real hardware behavior, sacrificing repeatability. A virtual test environment based on transactors, on the other hand, lets designers quickly reproduce a problem. Furthermore, the freedom from connecting the design under test (DUT) to a hardware test bed allows designers to execute the DUT from remote locations.

Equally important, by gaining full control of design clocks that aren’t sourced by the hardware test bed, debugging becomes easier and more efficient. By controlling the clock frequency, it’s possible to stop the model, read the memory content, force some registers or dump the waveforms. Debugging in an ICE environment requires hardware logic analyzers driven by the uncontrollable clocks coming from the test bed. The setup causes undeterministic behavior and compromises the debug ability of the DUT.

The whole verification perspective changes once designers experience transaction-based verification via emulation because being able to setup a powerful test environment free from cumbersome ICE hardware means easier and more effective debugging. The goal is the same — better design in less time — but the experience can be less challenging. In fact, within a few years, 80 percent of design teams will use transaction-based verification.

The EDSFair survey produced some other noteworthy results from respondents, most of who work for consumer electronics companies in Japan. Many wrote that they were planning to purchase emulators within the next six to 12 months, with applications ranging from ASIC validation to hardware/software co-verification. Interestingly, when asked which language they used, the overwhelming majority claimed Verilog, with very high-speed IC hardware description language (VHDL) a distant second. Verilog is the language of choice for testbench design as well.

Consumer electronics design teams are finding that a new class of emulators are fast, affordable and can execute billions of verification cycles as required for embedded designs in a short period of time. It is allowing them to plan more strategically and to successfully implement hardware/software co-verification. The results will soon be apparent to consumers who continue to demand better convergence in their electronics devices.

About the Author

Dr. Lauro Rizzatti, general manager of EVE-USA, has more than 30 years of experience in EDA and automated test equipment (ATE), where he held responsibilities in top management, product marketing, technical marketing and engineering. You can reach Dr. Lauro Rizzatti at lauro@eve-team.com.

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