Test Chip Collaboration Validates That Virtually Maskless SOCs Are Now Practical

Aki Fujimura, Chief Executive Officer, D2S Inc., Managing Sponsor of the eBeam Initiative
Moazzem Hossain, Chief Executive Officer, Fastrack Design, Member of the eBeam Initiative
Bob Smith, Vice President, Marketing, Magma Design Automation, Member of the eBeam Initiative

Mask set cost at 65-nanometer and below is limiting design starts. E-beam direct write (EbDW) technology has the potential to jump start design starts by virtually eliminating the need of photomasks for designs such as prototypes, derivatives and low-volume/high-value designs. However, throughput concerns have curtailed the use of EbDW for critical—and expensive—design data mask layers. Design for e-beam (DFEB) is a new design-for-manufacturing (DFM) approach that uses character or cell projection (CP) technology, combined with design and software techniques, to enhance the throughput of EbDW lithographic exposure. When applied to a 65-nanometer test chip design, DFEB can produce a design with an improved EbDW shot count, and thus improved throughput, without sacrificing the quality of design results.

E-beam: The Opportunity for a New Bridge

Traditionally, the mask has served as the bridge between design and manufacturing. However, if the goal is to reduce mask costs, another bridge is needed. EbDW machines, which can now project characters directly onto wafers, represent an opportunity to create a new, less costly bridge between design and manufacturing.

E-beam's strength is accuracy. Even at 65-nanometer and 45-nanometer, no optical proximity correction (OPC) or reticle enhancement technology (RET) is required.¹ However, e-beam's historic challenge has been its throughput time; it is orders-of-magnitude slower than standard optical lithography.

Variable-shaped beam (VSB) and CP capabilities help to address this limitation. VSB fractures the complex shapes of design features into multiple rectangles, each of which requires a separate exposure or shot from the e-beam. CP uses stencils to project a larger character in one shot (Figure 1).

Figure 1. VSB vs. CP

Illustration due to Hitachi High-Technologies Corporation

Advanced, CP-capable EbDW machines write directly on wafers without the need of a mask. At 65- and 45-nanometer, entire standard cells can fit within the projection area of these EbDW machines. Standard cells and random access memory (RAM), which can be converted to characters easily, now dominate system-on-chip (SOC) designs. These advances have resulted in a 2–5X improvement in throughput—a major step forward, but not enough to enable EbDW to be used for all critical design layers.

Recently, DFEB technologies and design techniques have been developed that speed up e-beam production a total of 10–25X over the traditional VSB method, depending on layer and design, making it practical for use on all critical layers of a SOC.

Design for E-beam

DFEB is a combination of software and design technologies that optimizes the design process to take maximum advantage of today's most advanced CP EbDW equipment to reduce shot count and, in turn, make virtually maskless EbDW production feasible.

Because they represent over 80 percent of the cost of a typical SOC mask set, DFEB is aimed at eliminating the complex computer-aided design (CAD) layers of the mask set. These layers contain design data that defines the function and performance of the SOC.

Using CP EbDW, characters are laid out in a stencil mask design that acts as a "mini reticle." Each cell's orientation that has a corresponding character on the stencil mask can be projected in one shot rather than in many shots, as would be the case in conventional VSB writing. Dozens to hundreds of characters can fit on each stencil. A CP machine may also have multiple character groups on a stencil mask; each character group can be exposed on the wafer by moving the e-beam without a time-consuming physical move of the stencil mask.

To achieve a 10–25X shot count reduction, DFEB changes the process of converting design features to characters from an inefficient "search and find" process for each design to a streamlined "take and optimize" operation with a stencil mask pre-manufactured per standard cell library instead of per design.

The EbDW process for any design can start only when the stencil mask is available. Currently, a taped-out design's features are converted to characters. The design is searched to look for the most commonly occurring patterns per layer. A stencil mask is then produced with those patterns.

Using DFEB, the standard cell design library is co-optimized with the stencil mask design. This DFEB overlay library contains shot count information and DFEB-optimized cell layouts. Co-design minimizes the shot count of designs using the library while maximizing use of the limited space that is available on the stencil mask. The stencil mask thus produced can be used for any design using that cell library, and therefore is ready before tape-out and even before logic synthesis.

Designers use the DFEB overlay library with the original design library. The DFEB design methodology uses shot count as an optimization criterion along with area, timing, power and yield during the synthesis process, employing currently available commercial synthesis products without modification.

DFEB impacts only the implementation phase of the design process. A systems designer operating above the unchanged register-transfer level (RTL) is unaware of any differences in designing for EbDW.

The DFEB methodology retains a design's "downward compatibility" for later processing with masks and standard optical lithography for large-volume production, if desired. Only the DFM/RET/OPC steps must be performed on the DFEB design to complete the design for mask production.

What Designs Benefit Most?

The designs that benefit most from DFEB are those that are most sensitive to reticle cost and manufacturing turnaround time: derivatives, prototypes and low-volume/high-value designs.

Derivative designs, which leverage existing design intellectual property (IP) to create multiple, differentiated versions of a single design platform, represent one of the most promising areas for the SOC market. With minimal additional design investment required, derivative designs can create a “long tail” of low-volume products that greatly increase the overall market for a given SOC platform. However, derivative designs can only provide this long tail if production costs are reduced.

The accelerated manufacturing cycle offered by EbDW and DFEB—without OPC, mask making, mask inspection and mask repair in the critical path—is especially attractive for prototypes. The faster a prototype can be plugged into the system, the sooner the debug process can start and the faster the product can get to market. DFEB also provides an ability to demonstrate (e.g., at a trade show) a working, battery-operated prototype system without the ribbon cables that attach to a fi eld-programmable gate array (FPGA) prototype board.

Prototypes also often change to correct mistakes, reflect changes in the netlist, or respond to changes in the specifications or market requirements. Usually, the second mask set is limited to less-expensive, metal-only changes; but an EbDW-based, maskless prototype need not be limited to metal-only fixes. Because of cost, in a typical mask-based cycle, necessary changes and potential improvements to a design tend to "accumulate" waiting for the next mask set. This tendency significantly delays revisions. In contrast, an EbDW-based prototype can be turned immediately because there is no fixed non-recurring engineering (NRE) cost for the mask.

Finally, low-volume/high-value designs, such as those for supercomputing applications or very specialized equipment, benefit from the drastically lower DFEB manufacturing costs. By eliminating the majority of mask layers required to produce these designs, the total cost of these traditionally very expensive chips can be cut significantly.

Ecosystem Collaboration to Validate DFEB Design Flow

A group of industry leaders collaborated to create a DFEB design methodology and prove that it could reduce EbDW shot count and thus improve throughput.

The subject design was a three-million-plus-gate 65-nanometer test chip containing 188 memory macros and one phase-locked loop (PLL) macro. The area spec for the design was a fixed floorplan footprint of 4.2 x 8.4mm². The design used a 65-nanometer low-power seven-metal layer process. The core had a frequency of 166MHz, and the external interface used for testing with an FPGA had a frequency of 162MHz.

The DFEB methodology (Figure 2) employed an industry-standard synthesis tool to re-target and optimize the test chip to the DFEB 65-nanometer overlay library. Other commercially available electronic design automation (EDA) tools were used for physical implementation, timing closure, final verification and tape-out.

Figure 2. DFEB Methodology

DFEB Design Flow

The DFEB design flow is very similar to established flows for advanced process nodes. The collaboration identified three areas where DFEB and standard design flows vary: DFEB overlay library preparation, floorplanning and synthesis/post-synthesis timing optimization.

DFEB Overlay Library Preparation

To minimize shot count, the test chip was implemented with a DFEB-optimized cell library—the DFEB overlay library. A commercially available physical implementation system was used to create abstracts from the graphic design system II (GDSII) DFEB library. The conventional standard cells in the library were assigned a "hide" attribute so the place-and-route tool would not use them.

DFEB Floorplanning

EbDW stencil masks have limited capacity. But each cell's orientation requires a different character except where symmetry can be exploited. To speed EbDW lithography throughput, the number of cells that can be shot using one character should be maximized. Therefore, the DFEB floorplanning methodology heavily favors standard cells of certain orientations and static random access memory (SRAM) macros of north-south orientations.

These preferences introduced additional criteria for floorplanning. Even so, the test chip's 4.2 x 8.4mm² footprint was met while avoiding routing congestion. Routing over the 188 memory macros was allowed for five metal layers and above.

Another difference in DFEB floorplanning is power planning. The DFEB methodology recommends the metal width be an integer multiple of 1.0-micron because the widest power wire that can be written accurately on the EbDW machine in use for this process is 1.0-micron wide. So a 1.1-micron wire would have the same shot count as a 2.0-micron wire. The estimated power and ground width requirement for four to seven metal layers was calculated accordingly. The power ring design also followed the DFEB metal width guideline and met the design rule check (DRC) and metal density rules.

Synthesis/Post-Synthesis Timing Optimization

The use of clock tree synthesis (CTS) was restricted to only the DFEB buffer and inverter cells. The CTS results for clock skew and insertion delay met specifications, with the skew less than 300ps and the insertion delay less than 3000ps (less than half the clock cycle).

DFEB Test Chip Project Results

The goals of the test chip project were to establish a DFEB design methodology and to confirm the reduction in EbDW shot count using this methodology while maintaining quality of results, in terms of timing, area and power consumption.

The project successfully established a DFEB design methodology through tape-out using commercially available design and verification tools.

Shot count analysis tools are available in every stage of the DFEB methodology. The final estimated shot count for the test chip using the DFEB methodology and the DFEB stencil mask characters represented a 10.6X reduction over the conventional method using VSB for metal 1, contact, poly and diffusion layers. Tables 1 and 2 show the post-synthesis and post-layout estimated shot count for the chip, respectively. The shot count analysis in the pre-synthesis stage is more conservative than the post-layout shot count analysis.

The DFEB test chip met the design performance, power and area goals. Tables 3 and 4 show the worst timing input and output paths, respectively. Although the timing was a few percentages off, it nevertheless met the tolerances for tape-out.

Table 1. Post-Synthesis Shot Count Analysis

Table 2. Post-Layout Shot Count Analysis

Table 3. DFEB Test Chip: Worst Input Timing Path Report

Table 4. DFEB Test Chip: Worst Output Timing Path Report

Generally, it is expected that a DFEB design may trade off some performance, power and/or area for EbDW shot count. The degradation is expected to be around 5 percent for most SOC designs and negligible for the majority of SOC designs, as was the case with the test chip. The most critical timing paths can be shot with VSB with only minimal impact on the overall shot count. Therefore, managing chip area has the most critical impact since area affects both performance and power. At 65-nanometer, the total area in most SOC designs is dominated by interconnect area. A 5 percent increase in the total area occupied by the standard cells for a given netlist can often be absorbed by increasing the cell utilization rate in the standard cell sections. For most SOC designs, the overall area, performance and power will be unaffected by the deployment of DFEB, as the test chip illustrated.

Virtually Maskless SOC Design Validated

DFEB is a new approach that merges design with manufacturing to enable the use of EbDW on all critical layers of a design. This new approach has been validated through a design chain collaboration, resulting in a proven DFEB design methodology. Results confirm a significant (10X) shot count reduction while maintaining design time, area and power performance. This shot count reduction provides increased EbDW throughput to make virtually maskless SOCs practical.

The DFEB approach is especially attractive for designs that are sensitive to reticle cost and manufacturing turnaround time: derivatives, prototypes and low-volume/high-value designs. These three types of designs represent a core of innovation and potential market growth for the semiconductor industry.

About the Authors

Aki Fujimura is chief executive officer of D2S Inc. Previously, Aki served as chief technology officer at Cadence Design Systems. Aki returned to Cadence for the second time through the acquisition of Simplex Solutions where he was president/chief operating officer and inside board member. Previously, he was an inside board member at Pure Software and was a founding member of Tangent Systems. He currently serves on the board of Coverity Inc. Aki received his bachelor's and master's in electrical engineering from MIT. For more information, go to www.direct2silicon.com.

Moazzem Hossain is president and chief executive officer of Fastrack Design, a member of the eBeam Initiative. Moazzem founded Fastrack Design Inc. in 2001. Moazzem has been in the industry for over 12 years working in EDA tool development and design services. Prior to founding Fastrack Design, Moazzem worked for Magma Design Automation Inc. as director of design services. He has over 50 technical publications and numerous patents in EDA and chip design. For more information, go to www.fastrack-design.com.

Bob Smith serves as vice president of marketing for Magma Design Automation, a member of the eBeam Initiative. During his career he has held marketing and business development management and executive-level roles at a number of EDA companies, including IKOS, Synopsys, LogicVision, InTime and Stratosphere Solutions. He was a member of the original team that launched Magma's first products in 1998 and is the co-owner of a small San Francisco-based winery. Bob holds an M.S.E.E. from Stanford University. For more information, go to www.magma.com.

References

¹In e-beam lithography, proximity effect correction (PEC) is required to correct for both back and forward scattering of electrons. The effects are small enough in the case of forward scattering and large enough in the case of back scattering that the complex interaction of adjacent features associated with OPC is avoided. Thus, character projection of a two-input NAND gate is stamped the same everywhere on the wafer using EbDW.

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