AccelerATE Solutions is a multi-platform test engineering service provider located
in San Jose, California. The company's mission is to leverage its extensive
experience and contacts within the semiconductor test arena to expedite its
customers' time-to-market. AccelerATE provides the following services to reduce
production costs: test pattern conversion, test interface development, test program
development, device characterization, failure analysis (if required), test program
optimization, sample production, deployment to volume manufacturing,
and test program conversion.
For additional information, contact:
Tom Nulsen
(T) 408-573-6066
(E) info@acceler-ate.com
(W) www.acceler-ate.com
Advantest's new T5385 memory test system for dynamic random access
memory (DRAM) wafer test delivers an unrivalled 768-device under test (DUT)
parallel test capacity and 533Mbps capability for increased throughput
and lowered cost of test. Ideal for high-volume wafer fabs, the new tester is also
equipped with a flexible pin configuration that supports diverse DRAM devices,
allowing tester pin resources to be optimally allocated for efficiency, reduced
touchdowns and improved throughput. Achieving improved efficiency per device
while scaling even higher in parallelism, the T5385 also delivers known good die
(KGD) for consumer devices to greatly improve yields for low-power double
data rate two (LPDDR2) and DDR3 multi-die and stacked devices. Enabled
by hardware and software advances, the T5385 offers a high-speed memory
repair analysis (MRA) system for DRAM and Flash memory wafer test that greatly
reduces test time.
For additional information, contact:
Greg Self
(T) 408-988-7700
(E) g.self@advantest.com
(W) www.advantest.com
Frost & Sullivan is presenting Amkor with the 2009 Global Advanced Electronic
Packaging Technology Innovation of the Year Award at their Growth, Innovation
and Leadership conference in Scottsdale, Arizona. The award is based on Frost
& Sullivan's analysis of the advanced electronic packaging market, where
Amkor's innovative, new products, such as through-mold via package-on-package
(TMV™ PoP), FusionQuad® and flip-chip molded ball grid array (FCMBGA),
were recognized for technical innovation and electronic packaging leadership. Each
year, Frost & Sullivan presents awards to the company (or individual) that has
carried out new research which results in innovation that has or is expected to
bring significant contributions to the industry in terms of adoption, change
and competitive posture.
For additional information, contact:
Lee Smith
(T) 480-821-2408 ext. 5381
(E) lsmit@amkor.com
(W) www.amkor.com
BroadPak, a premier provider of semiconductor package substrate design
and signal integrity services, introduced a revolutionary design methodology for
packaging the emerging 40nm node. With its core expertise in advanced,
high-performance substrate design and test, BroadPak is the only independent
substrate design center dedicated to silicon-package co-design methodology
for demanding applications where cost reduction and increase in performance
matters. Through unique miniaturization techniques, BroadPak provides an
unprecedented level of miniaturization for system-in-package (SiP) used in very
low-profile (VLP) applications.
For additional information, contact:
Farhang Yazdani
(T) 408-771-6622
(E) inquiry@broadpak.com
(W) www.broadpak.com
In response to customer demand for independent, flexible IC development
and supply engineering services, DATest expanded its offering to include IC
design, strategic production test, product engineering and
supply management. The expanded offering also includes
a new name and a head office, doubling the size of the
automatic test equipment (ATE) lab and allowing room
for future growth.
DA-Integrated is the
semiconductor industry's first and leading provider
of comprehensive IC development services, helping
customers optimize time-to-market, development
cost, cost of goods sold and product quality. Their highly
experienced team has provided solutions for a broad range
of applications and device characteristics. DA-Integrated
focuses on customer requirements and offers flexibility in technical scope
and commercial terms.
For additional information, contact:
Rich Mullen
(T) 508-242-9599
(E) richmullen@da-integrated.com
(W) www.da-test.com
Evans Analytical Group's (EAG) release-to-production (RTP) team provides
engineering service and support from early chip design to volume production
in the areas of test program development and product engineering; test time rental
on all major ATE platforms; reliability and environmental qualification;
electrostatic discharge (ESD) and latch-up testing; printed circuit board (PCB)
layout and hardware design; failure analysis; focused ion beam (FIB) circuit
edit and debug; electron microscopy; and equipment calibration and repair services.
EAG also has over 30 years of experience in bulk materials characterization and
surface analysis.
For additional information, contact:
Aram Sarkissian
(E) aram@eaglabs.com
(W) www.eaglabs.com
ISE Labs is dedicated to the growth of failure analysis capabilities to meet the
needs of customers. The company's failure analysis lab has recently brought in a new
team led by Dr. Dan Sullivan, formerly of Phillips and LSI. As well, ISE Labs
upgraded most of its equipment, including the installation of a new Hitachi S-4800
scanning electron microscope.
For additional information, contact:
Nahil Khayatt
(T) 510-687-2470
(E) nkhayatt@iselabs.com
(W) www.iselabs.com
MASER Engineering offers fabless IC manufacturers and integrated device
manufacturers' (IDM) design groups first silicon circuit edit using the
latest FIB systems. This service is now available with the most advanced system
for single-die consumer electronic (CE) work, DCG Systems' OptiFIBIV.
This latest generation of CE FIB systems is capable of front and backside
modification. It has a unique coaxial FIB/near infrared (NIR) optics column
and a Graphic Data System II (GDSII) data-controlled piezo table for backside
navigation to features in the first metal layers of 40nm technology devices.
Advanced endpoint techniques as well as accurate copper metal layer removal and
deposition of low-ohmic molybdenum and platinum conductors and silicon
oxide isolation layers give design groups the possibility to avoid multiple respins
and the increasing costs for sub-100nm masks. Time-to-market for new,
advanced ICs can be shortened when using this new facility.
For additional information, contact:
Kees Revenberg
(T) 31-53-480-26-81
(E) kees.revenberg@maser.nl
(W) www.maser.nl
Mfg Vision specializes in low-cost, straightforward yield management and
data analysis for large and small companies. The company's FloorVision product
helps customers achieve higher yields and more efficient manufacturing using
a very attractive Web-based tool. What distingushes FloorVision is its ease-of-use,
speed and collaborative attributes, taking advantage of Web 2.0. Fabless companies
can also now provide a revolutionary third-party FloorVision license to their
foundries to help resolve fab-related issues more quickly. Round-the-clock support
and regular seamless upgrades are part of the package when companies purchase
licenses for FloorVision.
For additional information, contact:
(E) info@mfgvision.com
(W) www.mfgvision.com
MVTS Technologies' business model includes partnering with original
equipment manufacturers (OEMs) of ATE to provide a transition plan for the support
and availability of legacy and discontinued equipment. While each OEM relationship
is different, all provide ATE users with a resource for capacity expansion and
support for maturing ATE.
Specifically, MVTS provides services
such as parts repair, labor and field service, tester maintenance agreement
support, tester rental, application services and regional facilities to make newer
generation testers available for engineering and product development. MVTS also
purchases idle or surplus equipment for inventory to support resale of these out-of-production equipment and parts. Utilizing the extensive internal inventory
expertise, MVTS offers users of this equipment a turn-key OEM-like buying
experience. The equipment is configured to match the needed requirement,
packaged with warranty, training, applications, installation and an extended
service contract.
For additional information, contact:
Lisa Bruhn
(T) 760-795-2516
(E) lisa.bruhn@mvts.com
(W) www.mvts.com
RoodMicrotec is the first independent test house in Europe with fully automated
monitored burn-in service. By investing in a fully automatic loading/unloading
system, RoodMicrotec is now able to execute the burn-in process automatically.
This increases quality and shortens processing time, and no manual steps are
necessary which optimizes process safety. The process can now handle high-volume
burn-in as well as safe launch activities. The automatic system has a throughput
of up to 5,000 devices per hour, which is 10x faster than manual operation. The
reduction in processing time leads to a significant reduction in total cost. Amid
the current market situation, this is essential and results in a clear competitive
advantage for the customer.
For additional information, contact:
Ute Höchstötter
(T) 49-711-86709
(E) info@roodmicrotec.com
(W) www.roodmicrotec.com
Using an industry-standard cost of ownership model, Scanimetrics has
saved 54 percent of semiconductor test costs. Scanimetrics' Wireless Test Access
Port (WiTAP™) test technology can test many times and at any time during the
fabrication process, making it ideal for wafer-level and SiP testing. On top of the
54 percent test savings, Scanimetrics has shown that using WiTAP™ also increases
product revenue by improving yield, saving on discarded product, reducing
chip size, steepening yield ramps and increasing time-to-market.
For additional information, contact:
Adeline Chiu
(T) 780-433-9441 ext. 306
(E) achiu@scanimetrics.com
(W) www.scanimetrics.com
STATS ChipPAC has introduced a new flip-chip technology that offers significant cost
savings over standard flip-chip packages, with price points well below wire bond
packages. STATS ChipPAC's low-cost flip-chip technology features an innovative,
routing-efficient interconnection structure and a simplified substrate technology
design coupled with improvements in assembly technology such as a cost-effective mold underfill process. The low-cost flip-chip technology also features a
true lead-free bump composition which has proven to be effective with the mold
underfill process. The first phase of low-cost flip-chip technology was qualified in
2008 and is in high-volume production today.
For additional information, contact:
Lisa Lavin
(T) 208-867-9859
(E) lisa.lavin@statschippac.com
(W) www.statschippac.com
