Risk Management in the Semiconductor Supply Chain

Santhosh Kumar M, Client Partner, Bristlecone Inc.

Innovation has been and continues to be the cornerstone of semiconductor companies. Until the year 2000, companies were focused on product innovation, but for over eight years, companies have focused on supply chain process innovation in addition to product innovation. This change in focus is not surprising, as it is the response to the changing semiconductor manufacturing landscape.

Today, most integrated device manufacturers (IDMs) use external partners for many of the business functions they previously performed in-house. Many of the newer semiconductor companies formed in the last decade began their journey as a fab-lite company. And almost all semiconductor companies formed today are purely fabless. The underlying driver of this outsourcing trend is the cost of manufacturing. Hence, the initial focus of semiconductor companies is on foundries and outsourced assembly and test (OSAT) partners. Semiconductor companies have benefi tted from the location of these partners' facilities in lower cost countries, and pure-play foundries and OSAT providers have achieved economies of scale by providing the same service to multiple semiconductor companies, which has lowered the overall cost of manufacturing.

Semiconductor companies have undertaken continuous business process improvements, outsourcing business functions beyond manufacturing operations. In response, suppliers and service providers have mushroomed around the world to provide specific business functions to these companies. These functions include: product/feature design; manufacturing operations, such as wafer fabrication, bump, probe/sort, assembly and test; warehouse and outbound logistics (through third-party logistics (TPL) service providers); human resources; and managing planning functions. It suffices to say that in today's world, a semiconductor company depends on a number of partners to get their product to market.

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Test Chip Collaboration Validates That Virtually Maskless SOCs Are Now Practical

Aki Fujimura, Chief Executive Officer, D2S Inc., Managing Sponsor of the eBeam Initiative
Moazzem Hossain, Chief Executive Officer, Fastrack Design, Member of the eBeam Initiative
Bob Smith, Vice President, Marketing, Magma Design Automation, Member of the eBeam Initiative

Mask set cost at 65-nanometer and below is limiting design starts. E-beam direct write (EbDW) technology has the potential to jump start design starts by virtually eliminating the need of photomasks for designs such as prototypes, derivatives and low-volume/high-value designs. However, throughput concerns have curtailed the use of EbDW for critical—and expensive—design data mask layers. Design for e-beam (DFEB) is a new design-for-manufacturing (DFM) approach that uses character or cell projection (CP) technology, combined with design and software techniques, to enhance the throughput of EbDW lithographic exposure. When applied to a 65-nanometer test chip design, DFEB can produce a design with an improved EbDW shot count, and thus improved throughput, without sacrificing the quality of design results.

E-beam: The Opportunity for a New Bridge

Traditionally, the mask has served as the bridge between design and manufacturing. However, if the goal is to reduce mask costs, another bridge is needed. EbDW machines, which can now project characters directly onto wafers, represent an opportunity to create a new, less costly bridge between design and manufacturing.

E-beam's strength is accuracy. Even at 65-nanometer and 45-nanometer, no optical proximity correction (OPC) or reticle enhancement technology (RET) is required.¹ However, e-beam's historic challenge has been its throughput time; it is orders-of-magnitude slower than standard optical lithography.

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