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3D IC Architecture and Business Model for High-density Memories

Sang-Yun Lee, Chief Executive Officer, BeSang Inc.
Dieter K. Schroder, Professor, Electrical Engineering, Arizona State University

Memory business models and device scaling are facing challenges due to high manufacturing costs, a low fab return-on-investment (ROI), a limited number of read and write cycles in Flash memories, and capacitor scaling limitations for dynamic random access memory (DRAM) cells. The cost for double patterning with immersion lithography and cost of ownership for next-generation lithography tools such as extreme ultraviolet (EUV) are increasing sharply.

Hence, emerging memories, based on new material and device concepts such as phase-change, magnetic, spintronics and resistive memories, are being developed. However, it is difficult for emerging memories to catch up to the density of conventional single-crystalline silicon memories because, fundamentally, the device pattern density depends on the minimum lithography feature size, not on materials. Further, material breakthroughs must be realized for these emerging memories to be successful before market introduction. Therefore, it is generally believed that the chance is slim for these emerging memories to penetrate majority memory markets in the near future.

To overcome these challenges to the memory business model and device scaling, low-cost, high-density memory cell stacking in three-dimensional (3D) ICs is promising. Unlike well-known 3D through-silicon vias (TSVs)—a package-level technology—the true 3D IC must be able to stack high-density, multi-memory layers sequentially on top of other device layers in a single chip at low cost using proven material and device technologies.

3D IC vs. 3D Package with TSV

3D TSV packaging is used for 3D image sensors and will be used for some memory device applications. Compared to printed circuit board (PCB) integration, TSVs can have short distance interconnects, leading to enhanced system performance. In addition, because they stack multiple chips, TSVs have excellent small form factors which are especially important for mobile devices. However, the integration level is limited to a few hundred interconnects per mm2, which is far less than single-chip integration levels which require millions of interconnects per mm2. Hence, TSVs have limited bandwidth, and their application is limited to the package domain. Furthermore, it is not obvious that TSVs can reduce the cost of memory devices and increase memory density.

The true 3D IC, or simply 3D IC, should have solutions for low processing cost, low die cost, unrestricted 3D interconnects with high bandwidth, and high-density memory cells. Therefore, 3D ICs can overcome Moore's Law and extend the pace of memory scaling at low cost. The concept is shown in Figure 1.

Figure 1. Concept of 3D IC Architecture for High-density Memories

Unlike 3D packaging, which is parallel processing of multi-chips and stacking them in the vertical direction, 3D ICs are formed by sequential processing of functional blocks in the semiconductor manufacturing line. For example, as shown in Figure 1, optimized memory logic devices, or simply logic, are located on the surface of the semiconductor substrate, reducing the area of non-optimized logic on the 2D IC, and then high-density memory cells are placed sequentially on top of the logic block, leading to more die per wafer thanks to functional block stacking. For 3D ICs, die cost saving is more important than a small form factor. If the process steps for memory cell implementation in 3D cannot be reduced, 3D ICs cannot overcome the high manufacturing cost and low fab investment ROI.

Memory Applications for 3D ICs

In general, the memory cost per bit can be reduced through memory cell size shrinkage. However, memory cell shrinkage requires new tool investment and resource investment for new technology and material development. 3D IC architecture allows for the implementation of next-generation memory devices with currently available tools and technologies.

In particular, capacitor shrinking is the bottleneck of DRAM cell size reduction. Stacking the capacitors along with access transistors on top of memory logic is effective to introduce next-generation DRAM chips without tool and resource investments for next-generation capacitor development because the 3D IC architecture allows for the stacking of more memory cells in the vertical dimension for a given silicon substrate area. Likewise, Flash memory can be implemented in 3D ICs through stacking Flash cell arrays on top of logic on the silicon substrate. Memory expansion is relatively easy for 3D ICs because memory stacking is a repeating process without significant redesign of the logic area.

Considerations for 3D IC Architecture

There are two crucial considerations for the 3D IC architecture for high-density memories. One is low manufacturing cost to minimize the cost per bit, and the other is to utilize proven technologies, tools and materials as much as possible to minimize fab investment, maximize ROI, reduce risks of new technology development and achieve fast time-to-market.

As process steps are added to implement memory cells in 3D ICs, the manufacturing cost rises. To minimize the cost per bit, it is very important to reduce the additional manufacturing cost for each memory layer. It is believed that the first memory layer won't increase the total wafer processing cost because 3D ICs are formed through the stacking of functional blocks. For example, DRAM manufacturing has about 10 extra mask steps for memory cell implementation. The 3D IC process locates these 10 mask steps from the bottom silicon substrate to the top of the logic. Hence, the total mask steps with the first memory layer are about the same. An additional DRAM cell layer is designed to use about six additional masks, representing about a 15 percent processing cost increment, while memory density increases 100 percent per each additional memory layer in 3D. Considering the sharp increase of manufacturing cost with double patterning using immersion lithography and EUV, the 15 percent processing cost increment per memory layer with old generation tools is likely the most affordable method to continue memory scaling, and low cost can be achieved with 3D ICs.

3D ICs for Silicon Memories vs. Emerging Memories

To overcome problems with memories, there are many activities in the industry and academia to replace silicon memories with emerging memories. However, emerging memories have not yet been successful because compared to emerging memories, silicon has an accumulated manufacturing experience of several decades, silicon processing technologies and tools are well established, silicon memory devices are fundamentally stable, and silicon dioxide is reliable and easy to use. Recently, some emerging memories have successfully demonstrated 3D stacking capability. However, a fundamental issue with emerging memories is not the 3D processing technology, but the quality of new and sometimes unproven materials. Without breakthroughs in material quality, emerging memories will be unable to compete with silicon memories in high-density memory markets, but research on emerging memories will continue and will be necessary for the future of the semiconductor memory industry. However, the chance that emerging memories will replace silicon memories in the near future looks very slim. Therefore, it is desirable for 3D ICs to use reliable silicon memory technologies based on metal oxide semiconductor field-effect transistors (MOSFETs) and existing tools.

Memory Device Functions with 3D ICs

Since simple memory cells are stacked on top of logic with proven memory cell structures (i.e., "one transistor plus one capacitor" cell for DRAM and one transistor cell for Flash memory), good device characteristics and high reliability can be achieved. Basic memory cell device functions such as read/write/refresh of DRAM and program/erase are shown in Figure 2.

Figure 2. Memory Device Functions of 3D ICs

New 3D IC Manufacturing Model for Memories

The semiconductor industry needs to find a way to minimize the tool investment for high and fast ROI. Without high growth and high profits, the semiconductor industry will quickly mature similar to the auto and airline industries. Due to the steep decrease of the average selling price (ASP), revenue growth of the memory industry is being slowed while the required tool investment increases sharply, leading the memory business to change its business model.

Figure 3 shows a new memory business model which utilizes 3D IC processing at a new fab, while old generation fabs process logic for memory devices. Traditionally, a fab processes wafers for about eight weeks and transfers the finished wafers to assembly and test. Fab ownership cost has reached $4 billion and continues to rise every year, making ROI from fab investment extremely difficult. For example, a fab with a $4 billion investment needs to make a $10 billion profit over the next four years to compensate the depreciation of existing fab tools if the total depreciation of fab tools takes four years. And reserve cash for the next-generation fab investment might be $6 billion in the near future. To make a $10 billion profit over four years, a company which owns an advanced fab may have a 25 percent market share of the $40 billion memory market with 25 percent margins for four years. It is very difficult to do this, and only a few top-tier companies can survive the memory business.

Figure 3. Current and New Memory Business Models Comparison

3D ICs for memory applications have two functional parts. One is the logic on the bottom and the other is the memory cells on top. The processing time for logic with about 30 mask steps is about six weeks, and the processing time for a memory cell with about 10 masks takes about two weeks. Because memory logic does not use advanced feature sizes, it can be processed in established fabs, and high-density memory cells can be processed at new but small fabs. In other words, for two weeks of memory cell wafer processing with the proposed 3D IC technology, a new $1 billion fab can have the same production capacity compared with a conventional $4 billion wafer fab.

Combining four times higher production capacity from a 3D IC fab (or one quarter of fab investment for 3D IC processing) and about four times more die per wafer with 3D IC technology, memory productivity can increase up to 16 times. Therefore, with 3D IC technology for high-density memories and the new 3D IC fab business model, the memory business can overcome the high fab ownership cost, low ASP and low fab investment ROI.


The memory business model and its innovation through miniaturization face significant challenges. Therefore, a novel 3D IC architecture for high-density memories with high productivity, low processing cost, low die cost, unrestricted 3D interconnects with high bandwidth, and high-density memory cells should be considered for allowing Moore's Law and the pace of memory scaling to be extended. A new memory business model using 3D IC processing will significantly reduce fab investment, maximize ROI and increase productivity sharply.

About the Authors

Sang-Yun Lee is the chief executive officer of BeSang Inc. BeSang is a fabless semiconductor company located in Beaverton, Oregon and a pioneer in 3D ICs. BeSang was named a top 60 emerging start-up by EE Times and a growth opportunity in the semiconductor sector by Frost & Sullivan in 2009. BeSang has been a member of GSA since 2007. You can reach Sang-Yun Lee at

Dieter K. Schroder is a professor in electrical engineering at Arizona State University. Prof. Schroder is an IEEE lifetime fellow and served as a distinguished national lecturer for the IEEE Electron Device Society from 1993 to 2007. He is the author of "Semiconductor Material and Device Characterization," one of the best-selling texts in the semiconductor field. You can reach Dieter K. Schroder at

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