High-performance, Non-volatile Memories:
And the Winner is …
Douglas Mitchell, Vice President, Sales and Marketing, Everspin Technologies
A universal memory fulfills every system architect's needs: a
single memory that is high-speed, high-density and non-volatile
and has unlimited endurance with long-term data
retention. Universal memory has been the elusive prize since bubble
and charge-coupled device (CCD) memories were thought to be the
answer in the late 1970s. Though these and other technologies have
come and gone, there is a new generation of memories looking to
claim the prize; but are these technologies any closer to meeting the
ever-increasing performance and cost requirements of the electronics
industry's demands?
Roughly speaking, computer systems partition memory into
three primary blocks: cache memory tightly coupled to the central
processing unit (CPU), main memory managed by a memory
controller and code/data memory managed by an input/output
(I/O) controller. Currently, cache and main memory are thought of
as being solid-state, while the code/data memory is a form of disk
or disk array, historically rotating but moving toward solid-state.
Cache memory is usually fast, small, integrated into the CPU and
implemented with static random access memory (SRAM). Main
memory is larger and slower than cache and is usually implemented
with dynamic random access memory (DRAM). Both of these
technologies are volatile, losing data when power is removed.
Figure 1 demonstrates memory requirements within a generic
system hierarchy. In today's systems, the working memory is fast
but usually volatile. In some cases, these memories or portions of
them are made non-volatile by adding battery back-up in the form
of uninterruptable power supplies or dedicated battery subsystems.
System architects use code/data storage for information that must
be retained when power is removed while requiring much higher
densities. Code/data storage memory is non-volatile, typically
implemented as a rotating disk or solid-state Flash, and may have
additional battery-backed RAM. In all cases, compromises are made
to support the specific function.
Figure 1. Memory System Architecture
Block diagram representation of a generic computer system hierarchy.
Rotating disk drives deliver the densities and non-volatility but
with much slower performance than SRAMs and DRAMs. New
solid-state drives (SSDs) using NAND Flash exceed rotating media's
performance but suffer from reliability concerns. SSDs may use other
semiconductor memories such as SRAM or DRAM to improve
performance and reliability. High-performance battery-backed
DRAM caches provide additional throughput and data integrity
improvements to storage systems.
SRAM, DRAM and Flash have become industry-standard
solutions to this wide range of memory requirements. SRAM and
DRAM are both volatile, losing data when power is removed.
SRAM can have synchronous, wide-word interfaces for very fast
access or easier-to-use asynchronous interfaces for general-purpose
applications. Batteries are used to make them "non-volatile," but
these memories still carry reliability, wear-out and environmental
limitations. DRAM is available with various high-performance
interfaces but requires continuous power to operate. Flash memory
and its technological cousin electrically erasable programmable
read-only memory (EEPROM) have made great strides to increase
density while reducing costs, but as these attributes improve, data
retention and endurance suffer. Slow write speeds continue to be
Flash's Achilles heel. Is there a technology on the horizon capable of
becoming the universal memory?
Four technologies currently in development have the potential of
fulfilling many of the characteristics required by a universal memory:
phase-change random access memory (PRAM), resistive random
access memory (RRAM), ferroelectric random access memory
(FeRAM) and magnetoresistive random access memory (MRAM).
Each attempts to implement a combination of process and design
technologies where data is written directly to the memory cell to
achieve high speed, high density and low cost while incorporating
non-volatility with robust endurance and retention characteristics.
A detailed comparison of performance features for each of these
technologies is appropriate for later discussion. This analysis is
intended to briefly overview the characteristics of each technology by
highlighting the promise for each in the marketplace and where the
technologies best serve a system solution.
PRAM is based on the ability to switch a chalcogenide material
(generally an alloy of germanium, antimony and tellurium) from
a crystalline state to an amorphous state and back by applying
various levels of current to the storage element, resulting in higher
or lower heat in the storage element. The storage element's data
state is sensed by measuring the resistance of the element after it has
stabilized into its crystalline, low-resistance or amorphous, high-resistance
state. PRAM has the characteristics of being bit-level
programmable, reasonably fast to read and write, and has endurance
superior to current Flash products. It does, however, suffer from
sensitivity to high temperatures, which make it difficult to use in
harsh environments and may require programming after being
assembled into systems using high-temperature solder processes.
Although PRAM development has been active since the 1970s,
recent developments indicate that commercial products over 100Mb
in density may be available soon, but with performance compromises
that limit endurance cycling to one million cycles and write cycle
times to slower than 100ns.
RRAM is based on the ability to switch the characteristics
of certain materials by applying current pulses that change the
crystalline structure, resulting in a change in resistance. A number
of alloys are being studied that exhibit these characteristics. This
technology holds the promise of a very small cell size built on
sub-30nm complementary metal-oxide semiconductor (CMOS)
processes, resulting in large memory densities. The non-volatile
memory element would rely on perovskite-oxide thin-film materials,
advanced photolithography processes and diode switching (instead of
transistor switching) to create very small memory elements. Progress
has been made on developing memory arrays using these techniques
with the promise of achieving high densities and faster writes than
Flash. Endurance and speed performance, however, are not yet
capable of meeting mainstream memory requirements. Current
solutions are demonstrating write cycle times in the microsecond
range with million-cycle endurance.
FeRAM is built with a cell structure similar to DRAM which uses
a one-transistor and one-capacitor storage element to retain charge.
FeRAM replaces the DRAM charge storage capacitor dielectric with
a ferroelectric material, typically lead zirconium titanate (PZT),
strontium bismuth tantalate (SBT) or bismuth lanthanum titanate
(BLT). The crystalline ferroelectric material will orient its electric
dipole in one direction or the other based on the application of an
electric field to the capacitor plates. After orientation to a "one" or
"zero" state, the bit can be read by applying a voltage to the cell and
sensing whether a pulse is generated if the cell is being switched to its
opposite state. If not, then it was already in the sensed state, say a 0;
if so, a pulse is created by the dipole switching, indicating a 1. If the
cell did switch states, it must be restored to its original state before
further operation. Low-density FeRAM has been in commercial
production for many years but has suffered from the inability to scale
to densities higher than 4Mb. It has moderate speed and limited
read/write endurance, although far better than Flash. There is little
indication that FeRAM has enough industry support to achieve
significant improvements required to break through these limitations
to allow it to participate in high-volume applications.
MRAM has emerged as the most promising of these memory
technologies for approaching the needs of many applications in
the system hierarchy. Currently, commercial MRAM products
are shipping into the marketplace, establishing the technology's
viability as a production technology capable of meeting demanding
performance requirements. The MRAM memory cell stores data
using a magnetic tunnel junction (MTJ), a small device having two
ferromagnetic layers separated by a thin dielectric layer. It has two
stable magnetic states, one with the layers polarized in the same
direction and the other with its magnetization directions in the
opposite direction or anti-parallel. The resistance of the MTJ is low if
they are parallel and high if they are anti-parallel. Reading an MRAM
bit is accomplished by sensing the resistance of a small current passed
through the MTJ.
There are two major types of MRAM that are being commercially
pursued: toggle MRAM and spin-torque MRAM. Each uses a
different technique to write the memory bits. The write operation
for a toggle MRAM is accomplished by passing currents through
adjacent copper lines to generate the specific magnetic field pulses
needed to reverse the magnetization state. Only bits at the crosspoint
of two write lines will receive the correct pulses to be written.
Other bits in the array do not see the appropriate pulses and will
not change state. This write scheme is non-destructive and allows
random access of any address in the array. High volumes of toggle
MRAM are shipping today into demanding applications such as
storage, industrial automation and energy management systems.
In spin-torque MRAM, the magnetic state is switched by using a
magnetic field from current passed directly through the MTJ, rather
than the field generated from electrically isolated current lines. The
spin-torque effect switches the device to the parallel state when the
current is passed in one direction and to the anti-parallel state when
the current is reversed. This type of switching eliminates one of the
current carrying lines, enabling a more dense architecture with a cell
size comparable to DRAM. While toggle MRAM will continue to
scale to higher densities, spin-torque MRAM provides the promise of increased density, lower cost and lower power. The spin-torque
effect begins to be practical for dimensions below 100nm, and the
required current decreases as the area of the bit decreases. With
smaller technology nodes becoming increasingly attractive, this and
other factors make 65nm the approximate entry point for spin-torque
MRAM. Spin-torque MRAM has created broad interest and
is currently in development by a number of established and start-up
companies.
Key attributes for both types of MRAM result from data being
stored as a magnetic polarization. Non-volatility is inherent because
magnetization does not leak away with time-like electric charge.
Read/write endurance is unlimited because there is no known
wear-out mechanism related to switching a magnetic polarization.
No matter how many times the magnetic polarization is reversed it
always alternates between the same two stable states.
Figure 2. Capacity vs. Write Cycle Time
Maps speed and capacity to working memory,
code storage and data storage applications. |
Figure 3. Endurance vs. Write Cycle Time
Maps speed and endurance to working memory,
code storage and data storage applications. |
After mapping the capabilities of these emerging technologies, it's
clear that each technology has a place in the system hierarchy; but the
most demanding "working memory" applications require fast cycle
times and very high (infinite) endurance, pointing to MRAM as the
only viable non-volatile candidate in the near term. Additionally,
as the family of MRAM products continues to increase in densities
while achieving lower costs through the development of next-generation
toggle, then spin-torque products, MRAM technology
will capture more of the code and data storage segments of the system
architecture.
About the Author
Douglas Mitchell is vice president of sales and marketing at Everspin Technologies
in Chandler, Arizona. He holds a B.S.E.E. from the University of Texas in Austin
and an MBA from National University in San Diego. Mr. Mitchell has more than
30 years of experience in the semiconductor industry.
Back to Articles Home
