Overcoming DRAM Scaling Challenges:
Floating-body Memory Technologies, a
Leading Contender for High-density and
Embedded Memory Applications
Dr. Pierre C. Fazan, Chairman and Chief Technology Officer, Innovative Silicon S.A.
Scaling the conventional 1-transistor/1-capacitor (1T/1C)
dynamic random access memory (DRAM) bit cell or the
traditional 6-transistor (6T) static random access memory
(SRAM) bit cell below the 40nm node dimension represents a serious
technical challenge. In the area of DRAM bit cell scaling, contacts,
device aspect ratios and capacitor materials are all approaching
manufacturing limits. For SRAM bit cell scaling, variability and
leakage issues impose severe constraints and may limit 6T historical
cell scaling. Recently, new concepts have been proposed to address
these scaling and performance limitations. Among them, the
capacitor-less or floating-body (FB) memory cell is one of the leading
contenders to replace DRAM and SRAM memories for embedded
and standalone applications. This new technology is simple, uses only
conventional materials and is therefore fully compatible with CMOS
processes. Following the introduction of a technology exploiting a
bipolar junction transistor (BJT) operation and its recent evolution
toward three-dimensional (3D) devices and low-voltage operation,
capacitor-less RAM cells are now well suited to replace standalone
DRAM cells in sub-45nm memories.
History
Capacitor-less RAM technologies have significantly evolved over
the years. The first attempt at exploiting a single MOS transistor
to store information was made by Sasaki et al. of Fujitsu in 1978.
They integrated a P-channel metal oxide semiconductor (PMOS)
transistor with silicon-on-sapphire (SOS). By exploiting the FB
effect of a single N-channel MOS (NMOS) silicon-on-insulator
(SOI) transistor, a simpler and denser structure was proposed by
Tack et al. of IMEC in 1990. The device operations described by
these researchers were, however, incompatible with selective read/write operations and memory array implementation. That explains
why the technical developments in this area stopped after these
two first attempts. In 2001, Okhonin et al. of Innovative Silicon
demonstrated that by properly pulsing the device gate and drain,
a selective write/read operation was possible. This opened the door
to memory array implementation. This successful array-compatible
operation was also mentioned in 2002 by Ohsawa et al. of Toshiba.
As illustrated in Figure 1, by exploiting a BJT operation, Okhonin et
al. developed a technology exhibiting a higher signal-to-noise ratio,
a longer retention time, a better scaling ability and full compatibility
with future fully depleted (FD) 3D devices. The operating principle
allows capacitor-less RAM cells to replace not only embedded
DRAMs and embedded SRAMs, but also standalone DRAMs. This
drastically increases the market opportunities for such a technology.
Figure 1. BJT FB Memory Exploiting a BJT Operation vs. Regular
FB Memory Read Current and Retention Time
FB/Capacitor-less RAM Cells for Embedded
Memory Applications
As previously mentioned, the FB/capacitor-less RAM bit cell and
operating principle can be used to build embedded memories to
replace embedded SRAM or embedded DRAM memories. Figure
2 shows the various bit cell layout possibilities for planar transistor
structures. Embedded memories allow for the integration of cells
having a 25F2 to 45F2 area (F being the minimum feature size of
the technology). The cell area depends on the layout details. The cell
becomes smaller when adjacent cells share source and drain terminals,
and the cell becomes larger when one or two of the source and drain
terminals of adjacent cells are separated.
Figure 2. FB Memory – Various Bit Cell Layout
Figure 3 illustrates a 4Mbit embedded FB memory block used
as a cache SRAM replacement. It was developed for a 45nm high-performance
logic process on SOI wafers. Read and write latencies
of 2ns and 4ns, respectively, have been demonstrated. The memory
density including array and periphery is more than three times the
density of conventional embedded SRAM. Typical device retention
times of 100ms have been achieved as shown in Figure 4.
Figure 3. 4Mbit Embedded FB Memory Macro
Figure 4. Typical Embedded FB Memory Device Retention Time
FB Memory as a Standalone DRAM Replacement
The FB memory/capacitor-less RAM bit cell and operating principle
can also be used as a standalone memory replacement. Cell sizes of
4F2 to 8F2 are possible as illustrated in Figure 2.
Here again, the cell
area depends on the layout details. Figure 5 shows a scanning electron
microscopy (SEM) image of a 6F2 cell implemented in a 50nm
DRAM technology. As can be seen in the picture, two adjacent cells
share a common bit line or drain contact and have separated source
nodes. Word lines and source lines run parallel to each other while
bit lines are orthogonal. Such memory cells integrated with a DRAM
process exhibit a typical retention time of a few seconds as shown in
Figure 6.
Figure 5. 6F2 Standalone FB Memory Bit Cell Cross Section
Figure 6. Typical Standalone FB Memory Device Retention Time
Scaling, Roadmap and Challenges
At 40nm and below, excessive device leakage resulting from aggressive
device scaling severely affects both standby power and retention for
DRAM and SRAM technologies. This has prompted 3D device
structures to enter the various standalone memory technology
roadmaps. These 3D structures also provide a benefit to FB memory
cells and enable source and drain doping profile engineering to
control and improve cell electrical performance. Due to its unique
compatibility with FD devices, FB memory technology is fully
portable to all forms of 3D device architectures such as fin-shaped
field-effect transistors (FinFETs); multiple-gate FETs (MuGFETs);
surrounding gate transistors (SGTs); and tri-gate, vertical double-gate
and gate-all-around structures. For example, Figure 7 shows the
programming window and retention time of an experimental 11nm
FinFET device.
Figure 7. Programming Window (Left) and Retention Time (Right)
for a 11nm FinFET FB Memory
For embedded applications, 3D structures are not necessary due
to the larger footprint available for the bit cell. It is also possible to
integrate capacitor-less RAM cells using planar transistors on FD SOI.
The main challenges with FB memory technologies are achieving
the targeted retention times required by the application, integrating
with a low-cost process for 3D implementations and operating at
low voltage to satisfy all reliability requirements. The retention times
demonstrated in Figures 4 and 6 satisfy the retention requirements
for the typical bit cell. Future publications will disclose more
information on 3D and low-voltage implementations.
The FB Memory Bit Cell: The Future of High-density
Embedded and Standalone Memory
Applications
For technology nodes below 40nm, standard 1T/1C DRAM and 6T
SRAM bit cells present huge scaling and manufacturing challenges.
Due to the simplicity and performance of FB memory with future
3D structures, it appears to be the ideal candidate to replace standard
RAM bit cells for future high-density embedded and standalone
memory applications.
About the Author
In 2002, Dr. Pierre C. Fazan co-founded Innovative Silicon, developing a new
SOI single-transistor memory technology. He acted first as chief executive officer
and is now chairman and chief technology officer of Innovative Silicon. From
1989 to 1997, he worked as process integration engineer and then as manager at
Micron Technology, Boise USA, focusing on DRAM process integration. In 1997,
he was named Professor at the Swiss Federal Institute of Technology, Lausanne,
EPFL, where he taught in the field of IC manufacturing. Dr. Fazan has authored
or co-authored more than 100 papers and has invented or co-invented more than
190 U.S. patents. Dr. Fazan has served as a member of multiple conference
program committees. He obtained his physics diploma and Ph.D. degrees at the
Swiss Federal Institute of Technology (EPFL) in 1984 and 1988, respectively. You
can reach Dr. Pierre C. Fazan at pfazan@z-ram.com.
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