An End-to-end Yield Optimization Solution
Dr. Yervant Zorian, Vice President and Chief Scientist, Virage Logic Corporation
The ever-increasing design and process complexity of today's
embedded memories drives the need for robust test, repair
and diagnostic solutions. Semiconductor companies are under
incredible pressure to reach volume production with new designs
in increasingly shrinking time windows, which intensifies the need
for better support for yield learning and production ramp. And add
to that all the low-power system-on-chip (SOC) designs requiring
multi-dimensional optimization, increasing the complexity and
embedded memory content per chip. The number of memory
instances has also increased along with their hierarchical distribution.
In addition, multiple embedded memory sources and embedded
test and repair solutions—all on the same SOC—create major
technological difficulties for designers.
In addition to design complexity, process complexity has also
become a major challenge. The higher susceptibility to resistive,
performance, bridging, parametric variation and other new fault
types requires expanded test algorithms to detect, repair and
diagnose these faults. A higher level of miniaturization requires better
support for yield learning and production ramp-up. The ability to
have on-the-fly monitoring and analysis of volume diagnosis data
for increased efficiency of post-silicon bring-up, system debug and
embedded memory characterization is now more critical than ever.
A powerful solution is needed to address these issues and provide
designers with direct access and interactive communication with
the internal circuitry of their SOC memory system, whether it is
an internally developed or third-party memory, so they can debug
and diagnose system issues more quickly during the chip bring-up
process. Having the flexibility of mixing memories from various
sources to meet specific design requirements, while using the most
advanced test and repair solution, will help in the development of
higher quality end products for their customers.
More faults are emerging at every new process technology—such
as resistive faults, performance faults, bridging faults, parametric
variation and so forth. To detect these faults, new algorithms are
needed at advanced process nodes to diagnose, debug and classify the
faults. Eliminating fault escapes will result in optimal product quality.
Figure 1. Fault Detection at Advanced Process Technologies
Other unique capabilities that designers need include the
ability to extract embedded memory contents, to perform multi-corner
characterization, and to assess reliability and temperature
dependencies. Users should be able to classify and correlate defects,
analyze redundancy utilization and precisely localize physical failures
by zooming into the physical structure and locations of memory
instances based on retrieved memory failures, as opposed to simply
reporting the logical address of failed cells. With this type of solution,
design and test engineers could dramatically simplify the chip bring-up
process, in addition to accelerating the process.
Figure 2. A Silicon Bring-Up Flow
Extending the value to the test floor for design and manufacturing
test automation, a solution that offers the capability to support
advanced process nodes such as 40nm would be desirable. And
a highly intuitive user interface to enable users to quickly create
complex test patterns and analyze silicon response results would
be key. It would also need to rapidly generate detailed reports,
hierarchically analyze, and quickly identify failure types and locations
as designs are readied for transition from first silicon to volume
manufacturing—analyzing large volumes of data and collecting and
classifying statistical failure data at the die, wafer and lot levels.
To do this, designers are going to need a solution that offers
advanced features:
- An optimal distribution of design-for-test (DFT) logic between
the soft embedded memory test and repair system and the
memory hard macro.
- Low clock frequency transitions to deliver greater power savings.
- A library of test operations and algorithms that target fault
mechanisms and defect types associated with shrinking
technology and leakage defects.
- A special user logic handshake interface that allows for easy
handling of multiple power domains and voltage islands on-chip.
Figure 3. A Complete RTL to Test Floor Embedded Memory Test
and Repair Solution
An example of a complete register transfer level (RTL) to test floor embedded memory test and repair
solution to address the needs of SOC designers and test and product engineers.
With advanced automation capabilities to interactively
communicate with the embedded test and repair system
infrastructure in a chip through a JTAG port for post-silicon bring-up,
system debug, diagnosis and characterization of embedded
memories, the extraction of memory contents, multi-corner and
multi-voltage characterization, precise physical failure localization,
defect classification and redundancy utilization analysis would be
possible—all from an engineer's desktop without utilizing expensive
automatic test equipment.
Summary
What designers really need is an end-to-end yield optimization
solution that includes intellectual property (IP), design automation
and manufacturing automation to address the design and process
complexity challenges they face today—from initial design
planning all the way through post-silicon bring-up and volume
manufacturing.
About the Author
Dr. Yervant Zorian has served as Virage Logic's vice president and chief scientist
since joining the company in 2000. Prior to Virage Logic, Dr. Zorian served as
a distinguished member of the technical staff at Lucent Technologies and Bell
Laboratories and chief technical advisor to LogicVision. Dr. Zorian also serves as
vice president of the IEEE Computer Society for Conferences and Tutorials and is
the editor-in-chief emeritus of IEEE Design & Test of Computers. He founded and
presently chairs the IEEE 1500 standardization working group for embedded core
test, and has authored over 250 papers and four books. Dr. Zorian has received a
number of best paper awards, is an honorary doctor of the National Academy of
Sciences of Armenia, is a fellow of the IEEE and is the recipient of the 2005 IEEE
Industrial Pioneer Award. Dr. Zorian received his master's from the University
of Southern California and a Ph.D. from McGill University. You can reach Dr.
Yervant Zorian at yervant.zorian@viragelogic.com or 510-360-8035.
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