Introduction to and Benefits of 3-D IC Technology
Herb Reiter, President, eda2asic Consulting Inc.
In the race for higher system performance, lower power, longer
battery life, lower cost, ease-of-use, etc., semiconductors have
routinely contributed to the rapid progression of systems,
primarily by shrinking system-on-chip (SOC) feature sizes. To put
this into perspective, 25 years ago, the industry was at 2.0μm CMOS
technology, advancing to the current 20nm gate length (a 100X
linear reduction), which has yielded both technical and economic
advantages for most applications. This evolution epitomizes the
industry term "More Moore," obviously referring to Moore's Law,
where the number of transistors that can be placed on an IC doubles
approximately every two years.
However, the "More Moore" trend is unlikely to continue without
significant technological intervention. Shrinking feature sizes can no
longer improve performance because rapidly increasing interconnect
delays more than compensate for the small improvements in transistor
speed. Further, charging and discharging the on-chip interconnects
consumes more power and adds to the increase in transistor leakage.
In addition, due to the significantly higher development and tooling
costs for 20nm SOCs, only designs with very high production
volumes will still be able to amortize the high up-front cost of design
and manufacturing.
A quarter of a century ago, power-hungry bipolar technology
reached its limits and stopped designers from building larger and
faster circuits. CMOS began to replace bipolar technology in many
applications and significantly reduced system power dissipation.
CMOS technology not only allowed for higher complexities, but also
offered lower cost and paved a new growth path.
Today, our industry is once again faced with the fact that the
biggest design challenge threatening progress is the rapidly increasing
power dissipation. Increasingly, semiconductor companies are
reviewing their "2-D SOC" roadmaps and are studying how and
when they will transition to a new paradigm to continue meeting
their customers' demands for smarter, faster, lower power and lower
cost circuits.
Sci-fi fanatics have always relied on the third dimension to create
new avenues for success. A number of leading-edge semiconductor
vendors are already moving beyond traditional 2-D design techniques
and are adopting the key advantages of utilizing the third dimension
in IC design. They manufacture larger ICs and sub-systems utilizing
package-on-package (PoP), system-in-package (SiP) and several other
3-D IC design approaches.
Benefits of 3-D design include the ability to combine proven
die manufactured in the process technology most suitable for the
specific function (e.g., logic, memory, analog, radio frequency (RF))
into larger configurations. This building block approach keeps
development cost low and minimizes risk and time-to-profit.
Continued research into how to best utilize the third dimension
to efficiently implement larger and larger systems with higher speed
and lower power resulted in the development of through-silicon
vias (TSVs). Similar to vias in printed circuit boards, TSVs connect
different layers—in the case of ICs in die form. TSVs offer significant
power savings and much better performance gains than any other
means of connecting stacked die. They also don't require high-drive
inputs/outputs (I/Os), saving not only power, but also die area and
silicon cost. TSV technology enables die stacking on the wafer level
and produces hundreds or thousands of die stacks simultaneously. As
manufacturing techniques mature, TSVs promise to add major cost
savings to the technical benefits previously outlined.
Die stacks interconnected with TSVs are already in volume
production (e.g., CMOS image sensors (CIS) in digital cameras and
memory chips on top of each other to manufacture larger memory-only
configurations). Both applications contribute to developing and
maturing cost-effective manufacturing techniques for a wide range of
applications. According to Yole Development, 3-D TSV wafers could
account for as much as 6 percent of the total semiconductor industry
and 25 percent of the memory market by 2015. The equipment and
materials markets for manufacturing TSV ICs are projected to reach
$1 billion by 2013 and 2015, respectively.
Currently, early TSV adopters must rely on very basic design
tools. They are forced to iterate their designs and build multiple
prototypes before reaching a production-worthy solution. To fully
take advantage of 3-D in IC design and bring 3-D/TSV-based
systems to market in a timely fashion, the currently available
electronic design automation (EDA) design tools and flows must
be expanded. Accurate modeling tools and techniques, 3-D process
design kits (PDKs), productive planning/partitioning tools, as well
as 3-D-aware implementation and verification tools are needed. Design
for 3-D testability is another challenge EDA needs to address. Also,
interoperability with today's 2-D flows and the emerging 3-D tools
and flows are essential because only then will IC and system designers
be able to efficiently and cost-effectively integrate multiple 2-D
SOCs into larger 3-D systems.
GSA's EDA Interest Group
To accelerate the development and adoption of high-productivity
EDA tools and flows, GSA formed the EDA Interest Group with
representatives from EDA vendors, semiconductor firms, IC design
services, research institutes and other industry organizations to
analyze long-term market needs and recommend how EDA vendors,
in cooperation with customers and partners, could meet these needs.
In 2009, the group decided to focus its efforts on tools and flows
to support the new and rapidly emerging 3-D/TSV technology. As
a first step, they developed a brief survey to better understand the
industry's plan for utilizing 3-D/TSV technology and requirements
for tools and flows. This survey is posted at www.gsaglobal.org/surveys/3-D/index.asp.
Results and Findings of GSA's Market Research Study
1. Respondent Characteristics – A total of 36 semiconductor
vendors responded with complete and meaningful answers. All
respondents expressed interest in 3-D/TSVs, and approximately
one-third are already involved in ongoing 3-D/TSV research and
development (R&D) efforts. Figure 1 shows the following:
- Eight of the 36 respondents are very large IC vendors,
mostly fabless or fab-light, focused on the consumer and
communications markets, and sell mixed-signal ICs. All
achieved more than $1 billion in revenue in 2008.
- Seven companies generated between $100 million and $1
billion in revenue in 2008, and these companies design and
manufacture mostly analog, RF and mixed-signal chips.
- Five firms generated between $10 million to $100 million in
revenue in 2008 and sell mostly ICs with microelectromechanical
systems (MEMS) or networking and wireless solutions.
- Five respondents work at design services or consulting firms
whose annual revenue is below $10 million.
- Eleven respondents did not disclose their name or company
affiliation.
Figure 1. Characteristics and Type of Respondents
2. Target Applications for 3-D/TSV Designs – Mobile Internet
devices (MIDs) are an obvious target segment to benefit from the
space, power and cost savings that 3-D/TSV offers. Cell phones were
identified as the primary 3-D/TSV target application. Netbooks,
Global Positioning System (GPS) systems and digital cameras were
chosen next. Thirteen respondents mentioned other applications
beyond MIDs, including fiber optics, wireless sensor networks, RF,
energy management, display control, automotive, wireline or "other."
Figure 2. Applications for 3-D Stacked Die Configurations
3. Drivers/Motivators for Using 3-D/TSV – Performance (20) is
the primary motivator for using this technology, while footprint
(19), combined with board space savings, is a close second. Cost
(16), power savings (14) and die size (12), combined with more
predictable yields, came in before reliability (8). Other drivers
mentioned by respondents include lower design cost/risk, better way
to integrate dynamic random access memory (DRAM) + logic, and
combining die from different processes.
Figure 3. Drivers/Motivators for Stacking Die
4. Products to Combine in a 3-D Stack – Practically all die stacks
will contain at least one layer of memory.
Figure 4. Which Functions Will You Integrate in a Die Stack?
This survey clearly shows that memory will be ubiquitous. The
ability to combine heterogeneous die allows designers to integrate
much more memory in a stack versus in a SOC, which makes 3-D
ICs both area-efficient and low-power.
5. Integration of Passives – In addition to mixing die from different
processes, 3-D stacks also allow the designer to integrate passives in
the stack (e.g., mount them on the substrate very close to the die
stack or add them to an interposer) and achieve very high-quality
inductors, LC tanks or blocking capacitors.
Figure 5. Integration of Which Passives in Your Stack?
6. How Many Die Will be Combined in a 3-D Stack? – While the
answers vary from two to six layers (also called "strata"), the lower
and the higher number of layers appear most likely.
Figure 6. How Many Die in Your Stack?
7. 3-D/TSV Design Services Initially – More than 33 percent of
respondents plan to use a design service to get started with 3-D stack
design.
Figure 7. Rely on a 3-D Design Service Initially?
8. Packaging for 3-D/TSV Stacks – 91 percent of respondents plan
to use flip-chip technology to mount 3-D stacks. Nine percent have
PoP in mind, while four percent mentioned quad flat package (QFP)
or simply "other."
Figure 8. Which Packaging Technology for the 3-D Stack?
Conclusion
While most semiconductor vendors replied to the application-specific
questions, only about 25 percent to 33 percent of respondents
(about 10) replied to the EDA questions. Therefore, the results
are not statistically significant and not published here. This clearly
indicates that 3-D/TSV design tools and EDA vendors' capabilities
for this segment are not yet widely known. EDA vendors as well
as their customers will need to invest in education and hands-on
designer training before the industry can fully benefit from 3-D/TSV
technology.
GSA's EDA Interest Group will continue contributing ideas and
efforts to accelerate EDA tool development and with it the market
acceptance of 3-D/TSV technology. EDA firms, semiconductor
vendors, outsourced semiconductor assembly and test (OSAT)
companies and others are invited to contribute to this initiative.
Contact Herb Reiter, EDA Interest Group chair, at herb@eda2asic.com or Kristen Pillans at GSA (kpillans@gsaglobal.org) to join the
EDA Interest Group or one of the technical working groups that will
be formed in early 2011.
About the Author
Herb Reiter is president of eda2asic Consulting Inc., a firm he founded in
January 2002. eda2asic focuses on introducing new EDA tools, intellectual
property (IP) and other products/services that help semiconductor vendors
reduce IC design time, power dissipation and unit cost. Prior to starting his
own firm, Herb worked at Barcelona Design, Synopsys and Viewlogic. Before
joining the EDA industry, Herb experienced for 20 years how important IC
design productivity is for the semiconductor industry. In his technical and
international business roles at application-specific IC (ASIC) and field-programmable
gate array (FPGA) vendors VLSI Technology and National
Semiconductor, Herb managed market research, new product introductions
and alliances. Herb has chaired GSA's EDA Interest Group since May 2008.
You can reach Herb Reiter at herb@eda2asic.com.
Back to Articles Home
