IP Innovation: At the Core of Consumer Electronics Design

Frank Ferro, Director, Marketing, Sonics Inc.

With the economy in the doldrums over the past two years, it might seem as if high-tech innovation would suffer as consumers cut back on discretionary spending. While there is evidence that consumers kept their money in their wallets, it's safe to say innovation is alive and well. A survey conducted by Booz and Company in October 2009 revealed that of 2,000 respondents 53 percent cut spending on consumer electronics devices, while only 22 percent made purchases. These figures parallel semiconductor revenue decreasing 10.5 percent in 2009, compared to 5.4 percent in 2008, according to Gartner Group. Good news is on the horizon, however. This year the trend is expected to reverse with an expected growth rate of 13 percent and a return to pre-recession levels by 2011.

But even with consumers' new frugality, there were several bright spots in the consumer electronics industry last year. The smartphone segment grew 13 percent when the overall cell phone market was down, and there were strong sales of netbooks. The growth in these segments can be attributed to business professionals desiring 24/7 connectivity, feature-hungry teens wanting iPhones and aggressive pricing on netbooks (taking some share from notebook PCs).

A new and highly anticipated device to feed consumers' need for broadband mobility is the slate computer. This device made a big splash at the Consumer Electronics Show (CES) in January 2010 and is expected to sell several million units this year. Clearly, it's innovation, not economics, that is driving the need for consumers to take their "desktops" with them wherever they go. Better device form factors, mobile Web sites and high-speed wireless networks are beginning to deliver this mobile experience.

With the advent of digital TV, many consumers took the opportunity to upgrade their analog sets. The results showed in strong sales of high-definition televisions (HDTVs) fueled by sharp price reductions. It is difficult though to predict how consumer devices in the home will evolve. For example, TVs and computers have long been expected to converge. But neither one has replaced the other—yet. With the amount of digital content available such as family photos, movies and music libraries, along with unique devices ranging from digital picture frames to iPods, PCs, HDTVs and game consoles, it's clear that this is a hotbed for innovation.

The good news for consumer electronics and semiconductor industries is that consumers have assimilated into their lifestyle this diverse set of products (e.g., smartphones, eBook readers, media players) and applications (e.g., voice, video, audio, graphics, social networking) that will continue to drive the need for new devices with higher performance and even more features. However, the public is demanding. It wants better Web browsing on smartphones, faster mobile broadband access, better battery life and the ability to browse the Internet on TV. Like spoiled teenagers, they want it all, but at a cheap price.

Moore's Law Helping and Hurting

These consumer demands are important, of course, to the original equipment manufacturer (OEM), but they will quickly trickle down to the semiconductor manufacturer because a large percentage of a product's overall capability falls on the system-on-chip (SOC). With the ability to pack multiple system functions onto a single IC, much of the knowledge base has shifted to semiconductor manufacturers, forcing them to provide complete solutions including hardware and software. They constantly struggle to stay profitable while maintaining chip, software and system teams, and usually only get paid for the hardware.

The drive to remain both competitive and deal with an unpredictable economy has forced companies to greatly reduce their engineering staff. OEMs have shed their chip teams, pushing the work onto the semiconductor manufacturer. Semiconductor teams have also been reduced, making it difficult to launch new SOC programs because they are struggling to finish on-going ones. To maintain competitiveness, timely execution is critical to secure top market share and, ultimately, profitability.

Lots of Functions in a Small Space

To further complicate things, the rapid advancement of process technology to 65nm and below has increased the number of functions that can be added to a single SOC. Even a medium-complexity SOC can have 30 to 50 individual functional blocks or cores in the system. These typically include the main processor, signal processor, custom processing engines, memory and input/output (I/O) blocks to name only a few. Some of the high-complexity SOCs can contain 70 to 200 cores. With this level of complexity, there are many new design challenges arising that SOC teams did not face in the past. These include how to connect multiple cores, how to manage the data flow, how to connect new and legacy cores with multiple protocols, and how to reuse the technology for subsequent projects.

Let's briefly look at a few typical SOCs. In an HDTV SOC, there is advanced signal processing (de-blocking, de-ringing, edge detection, scaling, de-interlacing, noise filtering, overlays, color space conversion and more) to make the picture quality acceptable. The bandwidth needed for this advanced level of processing is currently between 4.5 Gb/s to 5.5 Gb/s for high-end HDTV, and is moving to 9 Gb/s to 11 Gb/s for next-generation designs. To accomplish this data processing, an HDTV SOC typically contains two central processing unit (CPU) cores, a video decoder, a video encoder, a two-dimensional (2-D) graphics processor, an audio decoder, National Television Standards Committee (NTSC)/Phase Alternating Line (PAL) decoders and a wide array of peripherals.

Another good example is the mobile applications processor that is used in smartphones. These processors deal with multiple data types such as voice, audio, video and graphics. They also must support multiple operating systems and multiple applications. The speed of today's processors is about 800 MHz and is expected to run over 1 GHz in the next generation of smartphones to support 4G data rates, 1080p video, advanced graphics and voice over Internet protocol (VoIP). Many of these functions have their own dedicated processing engine, thereby increasing the number of cores in the system and adding a new level of complexity to accessing memory since all the cores are competing for bandwidth.

Enter the IP Industry

As SOC speed and complexity continues to increase, it is impossible for any one company to develop all the needed technology and successfully execute programs on schedule and at a reasonable cost. This is especially true given the reduction in resources and with many resources focused on software. So how do SOC teams remain competitive?

Intellectual property (IP) outsourcing has been one solution that has allowed companies, especially the smaller ones, to acquire technology that is not necessarily critical to their unique value-add. As various hardware blocks mature, it becomes difficult to differentiate products on these hardware blocks alone. At that point, a company needs to decide if it should make or buy the technology. Often, the faster a company can make this decision, the better off it will be. It will allow them to focus critical resources on the functions that will truly differentiate products. Delaying this decision due to not invented here (NIH) can prove a costly misdirection of resources.

Today, there are well-established commodity IP blocks that even the very largest companies license, including Universal Serial Bus (USB) or memory controllers and so-called star IP such as processors. Other IP blocks, including video processing engines and graphics engines, are growing in importance because these functions are required in many of today's consumer SOCs. Another important IP block is the interconnect, or the on-chip network, that connects all these processors and other IP blocks together. The on-chip network is important because it touches every core in the system. It is the glue or center of the SOC, and it ensures that everything comes together properly. It must be able to communicate to anyone's IP at anytime.

On-chip Networks Critical to the Solution

Once the licensed IP is combined with the internally developed IP, the challenge is to build a system that can quickly and easily take advantage of the blocks' performance. Connecting these cores is no longer an easy task. What was once thought of as a simple bus now requires the sophistication to manage complex data flow through the system, the ability to connect these IP cores together from different sources with different protocols and the ability to communicate with the system software.

The traditional way of designing the on-chip interconnect is no longer effective. Several companies supply building blocks of IP components for bus design, but the burden of assembling and verifying their operations is the responsibility of the design team. Moving from basic functionality to more sophisticated data flow functions such as quality-of-service (QoS), error management, firewalls and software interaction requires using an entire design team. Since companies are being asked to do more with less, making a serious technology investment in on-chip network technology may not be how they want to spend their critical resource dollars.

Design Time: Going from Months to Days

Given the time and energy that it takes to develop an on-chip network, the ability to replace all of these wires and functions with a single IP block has multiple advantages. Time of execution, for instance, is critical. Having the ability to only define what is at the edge of the network or the interface of each core is a much easier task than developing the actual network itself. Another advantage is that the IP will already have built-in capabilities for data management such as QoS, security and error handling. Advanced on-chip network functions can even include interaction with the software, including driver support and virtualization. Finally, the on-chip network IP block will provide tools that will allow for easy capture of the SOC and analysis for performance, gate count and power.

Let's look at an example to illustrate how easy it is to go from a block diagram to actual register transfer language (RTL). A low complexity design was chosen for Figure 1, but the same principles apply regardless of the complexity. This design has nine master cores or system initiators and 22 slave or target cores. Master cores in this system include the CPU, Moving Picture Experts Group (MPEG) decoder, tuner, and other key processor or input devices. Target cores include memory and a wide array of peripherals.

Figure 1. Media Player Block Diagram—Low-Complexity SOC

Figure 2 shows how to arrange each of these cores by function and protocol interface. The key in Figure 2 displays the various protocols of each core in the system. In this particular block diagram, the interface to the cores includes Open Core Protocol (OCP) and Advanced Microcontroller Bus Architecture (AMBA) interfaces, Advanced eXtensible Interface (AXI) and Advanced High-performance Bus (AHB).

The cores are grouped in a way that will maximize performance and minimize gate count. Cores are organized into masters and slaves that are connected via an interconnect matrix. Master cores can be connected directly to the interconnect matrix and given their own dedicated connection for maximum performance (typically the CPU) or via AHB master layers to optimize gate count (shown along the top of the interconnect matrix). The same is done with slave cores. Some cores such as memory are connected directly to the interconnect matrix and others are connected via AHB slave branches to maximize gate count (shown along the bottom of the interconnect matrix). The grouping of cores into various layers and branches is done to maximize data movement through the system and to optimize memory access.

Figure 2. System Block Diagram Organized by Function and Protocol

Figure 3 is a screenshot of an actual on-chip network capture tool that guides the user through this process. With this tool the user only has to define the type of interface on each core shown in the graphical interface (upper half). And information about how these cores are connected, clocking information and QoS is shown in the tabs (lower half). The tool also allows for optimization of the overall system either for gate count, performance or power. Without being an interconnect design expert, using this methodology literally cuts design time from months to days.

Figure 3. On-chip Network Capture Tool

Conclusion

The performance and complexity of SOCs will clearly continue to increase as consumers demand better broadband mobility and feature-rich products that are connected in the home. With this heavy convergence of technologies, most semiconductor manufacturers must rely on third-party IP to cost effectively compete in these markets. As a key platform methodology, on-chip network IP enables rapid execution of complex SOC designs and establishes a platform for reuse that greatly simplifies the next design, which is proving important to the industry. As well, this methodology allows design teams to focus critical resources on developing value-added features that give their products a competitive edge and provide the electronic capabilities consumers crave.

About the Author

Frank Ferro is the director of marketing for Sonics Inc. He has more than 25 years of experience in the semiconductor industry and has worked extensively in the communications and consumer electronics fields, with expertise in the areas of wireless local area network (WLAN), VoIP, cellular phones, personal computers and SOC architectures. Prior to joining Sonics, Mr. Ferro spent three years as the director of marketing at SyChip Inc., a subsidiary of Murata, with responsibility for WLAN and VoIP products. He also spent 22 years with Bell Labs, AT&T, Lucent and Agere Systems, working in WLAN, storage, cellular and digital signal processors. While at Lucent he lived in Japan for five years, where he worked closely with large cellular and consumer electronics manufacturers. Mr. Ferro holds an executive MBA from the Fuqua School of Business at Duke University, an M.S. in computer science and a B.S.E.T. in electronic engineering technology from the New Jersey Institute of Technology.

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