Integrated Power Management Platforms: The Entry of Fabless Design Houses to Power Management System Design
Dr. Shye Shapira, Director, Research and Development, Power Management Platforms, TowerJazz
Todd Mahlen, Director, Marketing, Power Management Platforms, TowerJazz
Dr. Avi Strum, Vice President and General Manager, Specialty Product Line, TowerJazz
The decades-long practice of scaling down transistor size
has allowed many systems to be fully designed on chips.
As electronic circuits have found their way into diverse
applications, the amalgamation of electronic components with the
logic platform "workhorse" has materialized in various flavors. In the
last decade, power management circuits have found their way into
integrated chips. It is useful to examine this process with historical
background, as it has bearings on the technical supply chain of power
management circuit production, which is rapidly changing.
The migration to integrated platforms occurs when several factors
exist. One factor is technical capability. Once the logic is sufficiently
dense, the platform can accommodate logic and other components
on the same die. Another factor is cost. The price difference of using
a board solution outweighs the price penalty of placing large power
devices on a high-density digital silicon platform. And at times, it
is also the actual chip size that will determine if it can or cannot fit
into a certain system (e.g., cell phone of a certain size). For power
management applications, the emerging trend of digitally controlled
power management circuits is also driving towards the integration
of drivers with high-density logic. An overall boost to this process is
the proliferation of portable devices and green practices that require
efficient power management capabilities.
Change in the Makeup of the Industry
The migration of power management technologies to foundries or to
the general domain is accompanied by manpower and tool migration.
Once the option to buy silicon fabrication exists, integrated device
manufacturers (IDMs) may opt to outsource the fabrication of
new products. It also allows for the creation of independent design
teams in the fabless model. Typically, management and engineering
experience first comes from IDMs and then directly from universities.
In the same manner, various internal design tools which have been
used to interface with the fabrication environment internally may
now be sold to third-party vendors and serve the fabless or fab-light/foundry interface. In parallel, new tools are constructed so vendors
may serve this interface. An example of such a tool is a metal routing
resistance calculator, which is very important in power management
applications.
Solidification of the Design House/Foundry Interface
The move to a fabless or fab-light/foundry model for power
management formalizes the design fabrication interface. In the case
of an IDM, design and production are within one company, allowing
for customization and flexibility within the organization. Once the
design/production interface migrates outside the company, design
groups may perceive a loss of flexibility in the silicon implementation
solutions. This may happen when encountering a first-generation
(G1) foundry power management platform bought from or co-developed
with an IDM. G1 platforms cater best to the original target
applications they were designed for. They may not be very effective
technically or cost/performance-wise in addressing a broader range
of applications. For example, G1 platforms with buried layers may
have very good isolation solutions for medium direct current (DC)/DC converter applications, but may be too complex in terms of layer
count and cost for light-emitting diode (LED) driver applications.
As shown in Figure 1, a second-generation (G2) advanced foundry
platform is more flexible in the performance/cost tradeoff and more
versatile in the scope of applications it covers. G2 developers work
hard to differentiate by producing flexible solutions that service a
broader spectrum of applications. To meet this challenge, one needs
to construct a platform that can be optimized for cost (layer count
and price) and performance (Rdson, gate charge (Qg), substrate
isolation and advanced features such as deep trench) for each
application. The resulting process will have a stratified structure.
At its base, the process will be simple but offer a high-performance
power management platform. Then, being as modular as possible, it
will allow for the addition of features to enable enhanced platform
performance.
G2 platforms contain differentiating front-end features such
as innovative, performance-enabling process design kits (PDKs).
Examples worth mentioning are voltage-scalable devices and models
enabling the optimization of on-resistance per operating voltage in a
continuous manner; metal routing resistance calculators; selectable
automated guard ring placement; and closed electrostatic discharge
(ESD) and latch-up characterization and methodology. Another
feature is a robust intellectual property (IP) portfolio including low-cost
non-volatile memory (NVM). Such an NVM solution requires
no additional process steps to remain on the high-performance cost
curve, and scales from several bits for trimming to tens of kilobits
for digitally controlled power management applications. Features on
higher echelons of the stratified platform require a more complex
process, but service applications requiring higher performance.
These include buried layer solutions for the isolation of high-current
applications with large inductive loads (e.g., motor drive DC/DC
converters with current higher than 1 Amp). Deep trench isolation
allows for a higher density placement of drivers and an enhancement
of isolation.
Figure 1. The Second-Generation Integrated Power Management Platform Mindset
"Writing the Book"
In the medium term, the formalization of the fabless/foundry interface
and the need to provide flexible solutions for power management
platforms requires a company to identify the correlation between
the required performance of a single device and the application's
specifications.
For a standard analog application conforming to a given
specification sheet, experienced analog designers can point to the 1/f
noise, mismatch, voltage and temperature variation they are willing
to tolerate for the components used in their design.
Power management applications have not been in the fabless or
fab-light/foundry domain for long, so such relations between the
component performance and the required application performance
are not always clear to the platform user. As an example, consider the
key factors in power circuit robustness, noise and latch-up isolation.
In many cases, design groups are familiar with their own developed
platform or with a foundry platform that was transferred from an
IDM. Their design experience teaches them which applications this
platform can successfully service. This understanding is based on
full design loops, not on individual component performance. It is
hard, based on this understanding alone, to predict how well this
platform will serve new applications with new specifications.
Thus, the separation of manufacturing from design requires
foundry and design engineers to "write the book" for devices. Device
parameters based on process features which were implicit or taken
for granted now need to be spelled out, and design groups need to
make a prejudgment on whether a circuit based on these devices will
meet specifications. This requires foundries to provide more detailed
characterization data for each component and a recommendation
as to how the platform may be used. A clearer definition and
understanding of the connection between a device's performance and
the technology it serves would allow for better decision making on
choosing the right level of process complexity for a given application.
("Is a buried layer required for this application, or can one just use
guard rings? And how many?")
Two questions concerning power management are addressed
below.
Will There Ever Be an Industry Standard for Integrated Power
Management Platforms as There is for CMOS Platforms?
As previously mentioned, the migration of power management
platforms to foundries will create a formal interface that drives
standardization. This trend is already observed today. A standard
compact model was chosen by the Compact Modeling Council for the
laterally diffused metal-oxide semiconductor (LDMOS) transistor,
the workhorse device of an integrated power management platform.1
The flow of tools into the public domain is also beginning. Metal
routing resistance calculators specific for power device routing are
being offered in G2 foundry PDKs and by new third-party vendors.
However, unlike analog and radio frequency (RF) technologies,
where the non-digital part is roughly the same size regardless of the
technology node, power technologies may differ greatly in a first-order
parameter (e.g., Rdson). A good device technology may reduce
Rdson (along with another figure of merit, Qg) and the size of the
power device driver, which may be 60 percent of the chip area. As
this parameter relates so strongly to cost, it inhibits standardization.
An implementation of a given design on foundry platform "A" will
almost always be preferred over an implementation on foundry
platform "B" if it results in a chip that is 30 percent smaller, even if
the foundry producing "B" has a stronger market presence and tries
to dictate a standard.
It can be predicted that due to the segmented nature of the power
management market and its ability to differentiate with parameters
directly related to cost, there may be some standardization for power
management platforms. However, this may only occur for certain
applications as they commoditize, but it will never be as complete as
standardization in digital CMOS.
Will There Ever Be a Full On-chip Solution for Power Management Circuits as
There is for Other SOC Applications?
The integration of power management technologies on a silicon
platform bears some resemblance to that of RFICs. Both technologies
rely on passive inductive and capacitive elements. In RFICs, these
components are much smaller in value (in the range of nanoHenrys
and picoFarads), and designers have learned to manage with inductor
quality factors between 10 and 20. This made full silicon integration
of RF components with logic and analog circuits possible since the
end of the 1990s. However, current integrated power management
applications require both the inductive and the capacitive parts to
be in the microFarad and microHenry range. Their quality factor
needs to be high to enable high DC/DC converter efficiency. Currently,
integrated power management ICs use discrete inductors
and capacitors which stay off the chip due to reasons previously
described. At times, these are accompanied by discrete and efficient
Schottky diodes. While there have been some demonstrations of
power management circuits with integrated inductors,2 there is still
much development needed to make them production-worthy, which
may take several years to achieve.
About the Authors
Dr. Shye Shapira manages power management platform research and development
(R&D) at TowerJazz. Previously at Tower, he managed mixed-signal RF
platform R&D and the modeling and simulation group. Prior to working at
Tower, he worked at Agere and Lucent-Bell Labs and was a research associate at
the University of Cambridge. Dr. Shye Shapira can be reached at shye.shapira@
towerjazz.com.
Todd Mahlen is director of marketing and business development of the specialty
business unit at TowerJazz. Before the merger with Tower, he served as director of
marketing for Jazz. Prior to working at Jazz, Mr. Mahlen served as the business
development/application engineering manager for PolarFab LLC and served
in application engineering for VTC Inc. Mr. Mahlen can be reached at todd.mahlen@towerjazz.com.
Dr. Avi Strum is vice president and general manager of the specialty business unit
at TowerJazz. Previously at Tower, he served as general manager of the design
center in Netanya, Israel and the CMOS sensor and NVM business unit. Prior to
Tower, Dr. Strum served as the president and chief operating officer of TransChip
Inc and served in various management positions for Intel and SCD. Dr. Strum
can be reached at avi.strum@towerjazz.com.
References
1 See the Compact Modeling Council Website, http://www.eigroup.org/cmc/and
http://www.geia.org/CMC-accomplishments
2 Thin-Film-Integrated Power Inductor on Si and its Performance in an 8-MHz
Buck Converter Wang et al. IEEE TRANSACTIONS ON MAGNETICS,
VOL. 44, NO. 11, NOVEMBER 2008 p 4098
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