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Cliff Hirsch, Publisher, Semiconductor Times

An inside look at innovative semiconductor start-ups

Although semiconductor revenues at large companies are reaching record levels once again, questions remain regarding the state of semiconductor start-ups. I am constantly asked if there is a future for semiconductor start-ups.

My standard answer as of late is that there is plenty of innovation and start-up activity at the "fringe." What do I mean by this? I think we would all agree that the days of start-ups creating huge digital systems-on-chip (SOCs) based on ever-finer device geometries are over. Today, start-up activity needs to be based on innovation, cleverness and new ideas—not throwing muscle and dollars at gates. In this "fringe" world, start-ups thrive. Here's a list of a few innovations being driven by today's start-ups: microelectromechanical systems (MEMS) in CMOS, enhancement mode GaN metal-oxide semiconductor field-effect transistors (MOSFETS), quantum dot-based mobile image sensors, physically unclonable ICs, solid-state optical lenses, beam-forming ICs, third-generation (3G) CMOS power amplifiers (PAs), junction gate field-effect transistor (JFET) technology and adaptive radio frequency (RF) PA linearizer ICs.

For this issue, my favorite companies actually are large digital SOC start-ups. Yes, I am wary for the reasons stated above, but these companies are standouts. Tabula and Tier Logic have both developed "3-D" field-programmable gate arrays (FPGAs); although, 3-D has a drastically different meaning for each company.

Tabula goes to market with its Spacetime architecture, which runs multiple times faster than the user application to pack FPGA user logic into time slots. Tier Logic moves configuration bits into a thin-film transistor (TFT) static random access memory (SRAM) layer for a FPGA or a single mask for an application-specific IC (ASIC) version, reducing the size of the interconnect, which solves cost and porting problems.

Both companies have impressive technology and will be successful. I think the market needs both solutions. My only consternation is what will "Xitera" (i.e., Xilinx and Altera) do? Are these companies going to take a piece of Xitera's business, chopping price as is the nature of the semiconductor business? Or are their devices significantly attractive to expand their market, which is the ultimate goal?

Tabula was founded in 2003 and has raised $106 million to date from Greylock Partners, Benchmark Capital, NEA, Crosslink Capital, DAG Ventures, Balderton Capital, Integral Capital Partners and SVB Capital, and anticipates one more funding round prior to an initial public offering (IPO). The company has over 100 employees.

Tabula's Spacetime 3-D programmable logic architecture uses time as a third dimension, dynamically reconfiguring logic, memory and interconnect at multi-GHz rates. The Spacetime compiler manages this ultra-rapid reconfiguration transparently. Tabula has over 80 patents granted around the Spacetime architecture, with over 70 pending. When compared to 40nm FPGAs, a 40nm Spacetime device will deliver 2.5x higher logic density, 2.0x higher memory density, 2.9x higher memory ports and 3.7x higher digital signal processing (DSP) performance.

Based on the Spacetime architecture and deployed on TSMC's 40nm process, Tabula's ABAX devices will range in density from 0.22 to 0.63 megaLUTs. All devices will have 5.5 megabytes of RAM, 960 regfile blocks, 480 large RAM blocks, 280 medium RAM blocks, 920 parallel inputs/outputs (I/Os), 44 phase-locked loops (PLLs) and 48 serializer/deserializer (SerDes). The A1EC06 adds 1,280 multiplier/accumulator blocks. Designed for a wide range of applications, ABAX devices will initially target the telecom, enterprise and wireless infrastructure markets.

ABAX A1EC04 samples will be available in Q3 2010 and will go into mass production in Q4 2010. Initial devices are already designed into tier-one customer applications.

Tier Logic was founded in March 2002 and has raised roughly $15 million to date from Matrix Partners and Walden International. The company is very capital-efficient, developing silicon, tools and a process technology and securing initial orders for less than $20 million. Tier Logic has 25 employees in Santa Clara, California and 25 in Colombo, Sri Lanka.

Tier Logic separates user circuits and configuration circuits into 3-D stacked layers. Reducing the configuration overhead from the base layers of silicon allows Tier Logic to produce smaller, denser, faster, lower power and more reliable FPGAs. In addition, once the design is stable, the programmable configuration circuitry layer can be replaced by a simple metal layer and turned into an ASIC version. Unlike any other type of ASIC conversion, the timing remains identical between the FPGA and ASIC.

Tier Logic's 3-D FPGAs have a 1.8 to 3.5x advantage in gate density resulting from two factors: smaller footprint due to 3-D shift and higher logic efficiency from more configurability. Tier Logic utilizes two interchangeable process techniques to fabricate configuration circuits. The FPGA family uses reprogrammable TFT SRAM for configuration, while the ASIC family uses a one-mask, hard-wired customer bit pattern for configuration. The company has already been granted more than 50 patents on fundamental
3-D circuit design, implementation, concepts and architectures, and has over 20 pending.

TierFPGA and TierASIC devices are fabricated in a 90nm copper CMOS process from development partner Toshiba. Over 20 real register transfer-level (RTL) designs from customers have already run through the conversion flow, achieving high utilization and beating competitors' timing.

Tabula
3250 Olcott St.
Santa Clara, California 95054
USA
(T) 408-986-9140
(F) 408-986-9146
(W) www.tabula.com
Tier Logic
2975 Scott Blvd, Suite 215
Santa Clara, California 95054
USA
(T) 408-970-9500
(F) 408-970-9599
(W) www.tierlogic.com

Cliff Hirsch (cliff@pinestream.com) is the publisher of Semiconductor Times, an industry newsletter focusing on semiconductor start-ups and their latest technology. For information on this publication, visit www.pinestream.com.

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