Hardware Emulation Proven to Reduce the Cost of Bringing a Chip to Market

Lauro Rizzatti, General Manager, EVE-USA

While the semiconductor industry laments the cost of getting products to market and bemoans increasing design complexity, crafty design teams are finding ways to beat these seemingly impossible challenges with a host of creative solutions.

In some cases, these design teams are relying on embedded software and not hardware as a product differentiator. Others are looking to the electronic design automation (EDA) market for tools that can deliver a solid and defensible return on investment (ROI). And those EDA companies whose products can meet ROI performance measurements have a far better chance of success and long-term survival.

The semiconductor industry is known for having short product life cycles, all the while being nimble enough to address fast-moving markets. This fast pace consistently produces tangible results, but studies show that being even three months late in product delivery can cost more than a quarter of the potential revenue. Market share gained by being first to market may outweigh any premium paid for investing in the EDA tools needed to complete the project on time and within budget.

That's why these considerations of affordability and the use of the best available EDA technology must be balanced with a business model of restraint, but with a nod to new architectural ideas and competent development efforts. The increased focus on ROI has forced many companies to think more carefully about their yearly budgeting, and design teams need to weigh the ROI performance measurement accordingly. In general, the EDA industry has found that its tool sales are driven by ROI, affordability and good value. Semiconductor companies must be able to justify the purchase.

For example, hardware emulation, also known as hardware-assisted verification, is one EDA tool making a resurgence. While such tools have been around for more than two decades, they used to be housed in big boxes, were excessively expensive and never achieved speeds in excess of 1 MHz. Slow speed had prevented their deployment as platforms for embedded software validation. Further, the combination of slow speed and a high price tag limited their adoption by large corporations, and they were used mainly for hardware testing of large microprocessor and graphics chip designs.

Conversely, the latest generations of hardware emulators are implemented in small enclosures, saving space, power and infrastructure costs. Best of all, they cost a fraction of the big boxes and execute at several megahertz—exceedingly fast by any measure. They now are considered universal verification tools that can be used across the entire development cycle, from hardware verification to hardware/software integration and embedded software validation. They can be used to accelerate an existing logic simulation environment and to increase the total verification cycles prior to tapeout.

These tools can be cost effective, if implemented properly, and can handle design sizes of up to one-billion or more application-specific IC (ASIC) gates at high speeds. With a lower overall cost of ownership than prior generations, modern emulators can help a design team reduce the cost of bringing a chip to market and achieve the solid ROI they're looking for.

Figure 1. ROI Benefits of Hardware Emulation

Hardware emulators are universal verification tools that can be used across the entire development cycle, from hardware verification, hardware/software integration to embedded software validation for solid ROI.

Let's consider today's chip design reality. Testing hardware and software together on the actual chip is difficult, time consuming and expensive. If the design team hits a hardware bug, it needs to re-spin the silicon, a costly proposition both in terms of time and budget. If the team hits a software bug, the bug may cause a pricey delay in getting the product to market. Co-verification of hardware and software at an early stage with the aid of an emulation system and before silicon availability is a viable and increasingly popular strategy for these reasons.

The ever-popular workhorse logic simulation is an excellent choice for debugging register transfer-level (RTL) code, while electronic system-level (ESL) simulation is helpful in starting embedded software validation before silicon. However, neither can test the integration of hardware with software. In fact, increases in design complexity and the explosion of embedded software require processing of billions of verification cycles in a short amount of time. Logic simulation is not up to the task because of its intrinsically slow execution time, and ESL simulation, albeit fast in execution, does not offer the hardware design accuracy to trace hardware bugs.

This is where emulation can help. At a speed of 10 MHz, the latest generation of emulation platforms can execute one-billion cycles on a 10-million gate design in a little more than one minute. They can provide full access to the entire design for quickly locating defects, whether in hardware or in software, and reduce re-spins and accelerate embedded software development.

As many design teams will attest, fast emulation has become a critically important verification component for large and complex systems-on-chip (SoCs). Today, emulation is used to test the hardware aspects of a SoC design and to verify the integration of hardware and the embedded software. It is possible to start RTL verification at the block level and move on to the system level as the entire design takes shape. Emulation can also co-verify the interaction of hardware and software once the full RTL design is complete.

This alone could justify an emulator's ROI. Hardware and software designers are able to share the same system and design representations due to combined software and hardware views of the design. With this information, they are able to work together to debug hardware and software interactions. They can track a design problem across the boundary between the embedded software and the hardware to find the problem.

Emulation's traditional use as a means for in-circuit testing has been expanded to where they now support complex test environments, including hardware description language (HDL) testbenches; transactional C++, SystemC or SystemVerilog testbenches or test models; and test vectors. Hard cores, such as those provided by ARM, MIPS and others, can be accommodated through a dedicated module as well.

And that's not all. Newer generations of emulation platforms have gone green with cutting-edge technology. These platforms consume far less power than their earlier, big-box counterparts because the power dissipation of a big-box emulator wastes energy to cool the rooms where they reside, resulting in a lower monthly energy bill. It also means maximizing energy efficiency and decreasing a company's carbon footprint, easing up on the power grid. The range of power consumed per box is about 1 kW for a 100-million ASIC gate green emulator. A big-box emulator with equivalent capacity consumes more than 10 kW.

Newer emulation machines have smaller footprints, physical dimensions and weight, and have fewer parts and components than big-box emulators.

The dimensions of a big-box emulator with a capacity of 100-million ASIC gates exceed 50x30x40 inches, while the size of a green emulator with equivalent capacity is less than 20x20x10 inches. The volume of 33 cubic feet for the big box compares to a volume of about two cubic feet of the green emulator. As far as the weight of each, big boxes weigh somewhere around 1,000 pounds, while smaller emulators weigh only 70 pounds for an equivalent configuration.

When multiple boxes are interconnected to increase overall design capacity, a 500-million gate design would require four large boxes—or 120 cubic feet of volume, about two tons of weight, more than 30 kW of power and adequate air cooling. An equivalent green emulator would occupy less than 15 cubic feet of space and weigh about 200 pounds, draining 5 kW of electricity with less air cooling requirements.

One obstacle to the widespread use of emulation has traditionally been the high purchasing price. Big-box emulators of the past were priced at tens of cents per ASIC-equivalent gate, preventing their deployment in volume and pervasive adoption.

Current pricing for an emulation platform varies, depending on capacity, speed and environmental requirements. Some more cost-effective emulators are priced at pennies per gate, while others start at about $1 per gate. All in all, this pricing makes them a great choice for a broad range of designs, regardless of complexities or topologies.

Overall, hardware emulation is a viable verification tool that can help design teams bring their chips to market on time and within budget, producing a solid ROI for any development project. While it's important to maximize the budget spent on capital expenditures, reaching high-volume shipments in time is even more critical to a company's long-term success. Using the right design flow, methodology and hardware emulation platforms will provide benefits across the product's entire development and improve ROI.

The EDA industry continues to be the foundation for the semiconductor industry. Those companies who can demonstrate that their products offer good value and a clear ROI should survive and emerge as the next-generation leaders of the EDA industry. The emulation sector, in particular, should produce a new set of leaders in the not-so-distant future.

About the Author

Lauro Rizzatti is general manager of EVE-USA. He has more than 30 years of experience in EDA and automated test engineering (ATE), where he held responsibilities in top management, product marketing, technical marketing and engineering. You can reach Lauro Rizzatti at lauro@eve-team.com.

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