Advantest introduced its scanning electron microscope (SEM)-based
critical dimension (CD) measurement system for photomasks. Advantest's
E3610 and E3620 CD-SEM advanced mask metrology tools enable photomask
manufacturers to measure the critical dimension of the miniature-sized patterns
in a photomask and assure accuracy in semiconductor manufacturing. These
systems offer the precision and linewidth repeatability required to provide
continuous yield improvement at the 65 nm and 45 nm production nodes, as well
as support for 32 nm and 22 nm process development. The best-in-class E3610
and E3620 utilize Advantest's unique electron optical column design, enabling
accurate CD control. They boast superior long-term operating stability and CD
variation of less than ±1 nm, and are backed by the Advantest brand and the
company's renowned worldwide support infrastructure.
For additional information, contact:
Greg Self
(T) 408-988-7700
(E) g.self@advantest.com
(W) www.advantest.com
Amkor Technology and Texas Instruments (TI) announced they have
qualified and begun production of the industry's first fine-pitch copper pillar
flip-chip packages—shrinking bump pitch up to 300 percent compared
to current solder bump flip-chip technology. Co-developed to lower the
packaging costs of IC devices with fine-pitch input/output (I/O) pad structures
of less than 50 μm, this proprietary technology platform also boosts
performance, making it ideal for wireless and embedded processing applications
based on plated copper pillar bumping and assembly technology.
Working together, Amkor and TI rapidly developed, qualified and deployed
this new package platform that will not only address TI's flip-chip package needs
for the next decade but will also serve as a game changer for the industry. This
new lead-free technology enables the use of flip-chip interconnection at fine pad
pitches (50 μm and smaller) using fine-pitch copper pillar bumping and a newly
developed assembly process which acts as the platform interconnect technology
for integration with next-generation advanced silicon nodes. It also typically
reduces substrate layer count as compared to standard area array flip-chip, yielding a
low-cost package solution. The package was developed for very thin die, which,
when combined with the low standoff height of the copper pillar bump itself,
reduces package height.
For additional information, contact:
Lee Smith
(T) 480-821-2408 ext. 5381
(E) lee.smith@amkor.com
(W) www.amkor.com
DA-Integrated is the semiconductor industry's first and leading provider
of comprehensive IC development and supply engineering services. DA-Integrated
features a full suite of tools and expertise of a fabless semiconductor
company, offered as pure-play services, complementing customers' core
capabilities.
Finding the right provider for production testing of low-volume
and high-complexity ICs is always a challenge, especially when global
capacity is constrained. DA-Integrated's test operations group has grown to
meet this increased demand. The company provides competitively
priced production capability targeted specifically at this market segment.
Access to support from the company's design, test development and supply
engineering experts enhances the service, making DA-Integrated the
world leader for engineering sampling, pre-production, reliability testing and
low to medium volume production.
For additional information, contact:
Scott Bulbrook
(T) 613-592-2233 ext. 227
(W) www.da-integrated.com
Evans Analytical Group's (EAG) release-to-production (RTP) team
provides engineering service and support from early chip design to volume production
in the areas of test program development and product engineering; test time rental
on all major automatic test equipment (ATE) platforms; reliability and environmental
qualification; electrostatic discharge (ESD) and latch-up testing; printed circuit board
(PCB) layout and hardware design; failure analysis; focused ion beam (FIB) circuit
edit and debug; electron microscopy (transmission electron microscopy (TEM),
SEM, dual-beam FIB/SEM); and equipment calibration and repair services.
Coupled with 30 years of experience in materials characterization and surface
analysis, EAG offers the broadest range of solutions of any commercial lab
network.
EAG offers its customers a highly customizable and flexible service
model. The company believes that each customer's needs require the
right combination of resources, and outsourcing cannot take a one-size-fits-all approach. Many of EAG's fabless customers rely heavily on EAG's
integrated model to support their product flow from conception to volume
production, requiring full engineering support across multiple disciplines
and services. EAG's larger fabless and integrated device manufacturing (IDM)
customers are utilizing this model to support specific projects as a compliment
to their own resources. With the breadth of engineering expertise and services and
continued commitment to investment in technology, EAG is the partner to keep.
For additional information, contact:
Aram Sarkissian
(E) aram@eaglabs.com
(W) www.eaglabs.com
Through the years, LingSen Precision Industries (LPI) has emerged as a leader
of semiconductor subcontract assembly in Taiwan. LPI's engineering and production
teams have earned a formidable reputation worldwide for providing high-quality
product lines and reliability in its total solution. LPI's assembly capabilities are
proven throughout the U.S., Europe, Asia and China. The company's deliverables
include micro-electromechanical system (MEMS) quad flat no-lead (QFN)
packages, MEMS pressure sensors and MEMS microphones.
The MEMS QFN package is a plastic encapsulated package with exterior leads
around the bottom periphery to provide short electrical connection to the printed
wiring board (PWB). The package also provides excellent thermal performance
by having the die attach paddle exposed on the bottom of the package surface to
provide efficient heat path when soldered directly to the PWB.
The MEMS pressure sensor is a wire-bonded and lid seal on pre-mold
leadframe packages, and can be used in medical instrumentation products.
The MEMS microphone is a wire-bonded and cap seal on substrate system-in-packages (SiPs), and can be used in communication and consumption
products.
For additional information, contact:
Lilian Lin
(T) 886-4-2533-5120 ext. 5174
(E) lilianlin@lingsen.com.tw
(W) www.lingsen.com.tw
MASER Engineering offers Safe Launch support to the automotive semiconductor
industry. During the first ramp-up phase of new ICs in automotive applications,
the manufacturer has to prove device durability. MASER Engineering supports
fabless IC manufacturers with extended monitoring of the devices during Safe
Launch burn-in. A dedicated setup will stress the devices beyond the
observable level with ATE final test. Chips with power dissipation levels of 1
watt or beyond are exposed to a power temperature cycling where long-term
stability is proven with multiple on/off starts at very fast linear temperature ramps,
up to 10 K/min. Both test methods are formulated in the dedicated automotive
standard Automotive Electronics Council (AEC)-Q100. MASER Engineering
is fully equipped to address all related qualification tests to this standard as a
service.
For additional information, contact:
Kees Revenberg
(T) 31-53-480-26-81
(E) kees.revenberg@maser.nl
(W) www.maser.nl
MVTS Technologies is a global full-service provider of refurbished ATE to the
semiconductor industry. MVTS provides support and service for a selection of legacy
Credence, LTX, Teradyne and Verigy ATE worldwide, configured and refurbished to
customers' specifications. With a global team of field service representatives,
MVTS is confident in providing each customer with maintenance, installations,
de-installations and repairs. In addition, the company has a broad range of
value-added services such as turnkey applications, subcontract printed circuit
board (PCB) repair and essential test cell consumables.
For additional information, contact:
Ross Martindale
(E) ross.martindale@mvts.com
(W) www.mvts.com
Presto Engineering, an International Organization for Standardization (ISO)
9001 company, delivers Design Success Analysis, comprehensive semiconductor
test and analysis solutions to IDM and fabless companies. Operating from
hubs in Silicon Valley and Europe, the company's business is focused on helping
to improve the speed and predictability of new product releases.
Presto combines unique technical expertise, extensive industry experience
and leading-edge ATE for system-on-chip (SoC) and radio frequency (RF), along
with reliability, FIB and failure analysis/fault isolation services to offer a complete
product engineering solution designed to complement customers' internal
resources.
During 1H 2010, Presto established new hubs in Europe focused on failure
analysis and reliability services (Normandy hub, ex-NXP lab) and ATE services,
covering test program development and engineering bring-up support for both
wafer and packaged parts (Grenoble hub).
Presto is now offering specialized RF characterization and testing services
from its Silicon Valley and Grenoble hub, covering wafer-level, packaged
part and multichip modules (MCMs). The company's lab has the ability to use
high-frequency test and measurement equipment (i.e., network analyzer, pattern
generator, bit error rate test (BERT)), as well as RF ATE (Roos Instruments
Cassini) supporting direct current (DC) to 100 GHz source and measure. Presto can
also assist with test program development, probe card design (GGB and Cascade
Pyramid) and automatic handler support. Presto's lab in Grenoble has the Verigy
93 K Pin Scale RF test equipment as well as 300 mm wafer probe support.
For additional information, contact:
(T) 408-434-1808
(E) info@presto-eng.com
(W) www.presto-eng.com
STATS ChipPAC's low-cost flip-chip (LCFC) technology utilizes copper
column bump to deliver a powerful packaging solution at a dramatically
reduced cost. LCFC technology delivers flip-chip packages at price
points below wire-bond packaging due to its innovative routing-efficient
interconnection structure, simplified substrate design and cost-effective mold
underfill process. The unique structure of LCFC when combined with copper
column bump achieves an even lower cost solution with higher routing
densities and is scalable to finer bump pitches. Copper column bumps enable
a higher I/O density with a much finer pitch between the columns than
standard solder bumps, along with a higher resistance to electromigration.
Although copper column is a hard bump material that can typically cause
damage to low-K (ELK) layers in finer silicon nodes, the LCFC interconnect
structure dramatically reduces the mechanical stress on silicon subsurface
layers, resulting in the elimination of the ELK damage phenomenon commonly
observed in sub-45 nm silicon nodes.
For additional information, contact:
Lisa Lavin
(T) 208-867-9859
(E) lisa.lavin@statschippac.com
(W) www.statschippac.com
