Q: As the complexity of today's electronic devices increases, chip design verification becomes more of a challenge. Please explain how Jasper Design Automation's formal verification solutions reduce risk and accelerate time-to-market for chip companies.

A: The Jasper difference is in the way we apply and deploy advanced formal verification solutions to meet the particular needs of our customers. Our solutions address a spectrum of design-critical verification challenges such as getting the architecture unambiguously right, enhancing design reuse, verification including low-power optimization, protocol certification and post-silicon validation. Deploying formal technology, from design inception through intellectual property (IP) exploration and even post-silicon, can greatly accelerate time-to-market and deliver a high return on investment (ROI). We often hear from new customers that formal verification can quickly root out bugs in designs that had previously been in verification for months.

Q: The verification obstacles encountered by system designers and chip designers are becoming increasingly similar, leading some to believe that the two groups will eventually merge. How does the use of formal verification benefit system designs?

A: The early use of formal verification for model system architectures before register transfer level (RTL) can provide benefits through the entire development cycle, spanning both hardware and embedded software. Formalizing an executable spec accelerates the design and verification of a chip and individual design components. High-capacity formal verification is also key for verifying hardware interaction with software, including the operation of softwareconfigurable registers, register assignments, and other softwareprogrammable hardware functions such as power control. Looking at the need for hardware/software codesign, and the marriage of hardware and software verification for systems, formal verification technology is critical. Formal verification, by its mathematical nature, is independent of complexity in a way simulation can never approach, and can verify complex interactions rapidly and comprehensively for hardware, software and systems.

Q: In a market where EDA start-ups and venture capital are scarce, Jasper Design Automation has launched reputable products as well as gained recognition for its innovative efforts. Amid a tough environment, what are the keys to success that has allowed a small company such as Jasper Design Automation to prosper?

A: Jasper thrives because we completely focus on delivering a flexible, broadly deployable solution, including support, which solves top customer problems directly. Jasper's architecture investment supremely lends itself to rapid innovations that we often develop in partnership with our customers. This is diametrically opposed to delivering a software package that ends up sitting on a shelf unused. Jasper also created a scalable business model to reflect its broad and demonstrable value. Thankfully, raising capital has never been a problem for Jasper due to the viability of our business model, our impressive customer traction, and making strategies and execution metrics transparent to our very sophisticated investors and board.

Q: As the current vice president of the Electronic Design Automation Consortium (EDAC), you have promoted the achievements of private EDA companies and showcased the significant return on investment (ROI) the EDA segment delivers to the semiconductor industry. Please describe EDAC's impact on the industry.

A: EDAC focuses on issues that individual EDA suppliers cannot address themselves. We have government lobbyists to ensure encryption, and export control regulations don't place onerous restrictions on our member companies and customers. We have also developed an anti-piracy initiative to protect the interests of EDA customers and suppliers. The real victims of software piracy are the paying EDA customers who find themselves at a distinct disadvantage when they are selling against competitors who can produce parts more cheaply by using stolen software. As well, EDAC financially and strategically supports the annual Design Automation Conference (DAC), providing a high-quality global technical conference where the EDA community can share ideas, meet with customers and display the latest innovations in our field.

Q: The EDA space saw quite a bit of M&A activity in 2010, with the larger companies acquiring the smaller players inside and outside the sector. Do you believe this is the best course of action (i.e., acquiring smaller players), or do you believe they should be partnering with other EDA companies or consolidating with other large players?

A: Consolidation is a fact of life in EDA as it is in the entire semiconductor industry. However, I do not believe the acquisition of premature start-ups is the best strategy for the EDA sector's growth. Many EDA start-ups are positioned for an acquisition by a larger player before they have delivered sustainable value to the market and significant adoption of their technology has occurred. In these cases, when the prevailing exit strategy is solely to gain enough traction to be acquired, there may be a few winners, but there will be a lot more fire sales. Early exits often lead to infant mortality of critical innovations.

Jasper and my previous companies have had the staying power to drive substantial adoption of missionary solutions, making sure they have real world applicability and sustainable ROI. Once technology, customer adoption and scalability risks are eliminated, then only can a business with real value to investors, customers, employees and potential M&A candidates be built. This raises a company's valuation regardless of a choice of exit strategies.

Q: Many industry professionals have voiced the need for cooperation within the EDA industry to create an open ecosystem for the design community. With an increased group effort, what area do you feel the industry should be focusing on?

A: Jasper is very enthusiastic about unified standards, and we are active in organizations such as Accellera that promote standards for EDA, semiconductor and IP vendors. It's much more valuable for EDA suppliers to focus on tool innovation rather than support fragmented "same but different" standards, and our customers who want to use best-in-class tools from multiple vendors suffer too if interoperability is not ensured.

Q: Jasper Design Automation has openly advocated for the EDA industry to leverage the advantages of parallel computing, an issue that has been highly debated by the community due to technical challenges. Explain the value parallel computing provides the industry.

A: By leveraging the advantages of parallel computing, expensive calendar time and engineering labor is exchanged for relatively inexpensive computer time, maximizing throughput. With a new-generation EDA platform, Jasper has a huge advantage and is leading in this area because our architecture is designed for scalability and parallelization. We view parallelization as a way to shrink schedules and user efforts, delivering inherent ROI for customers. For example, think of how much engineering productivity is unleashed when a verification run is slashed from 10 hours to just one hour!

Q: As a verification expert, what questions or complaints are you hearing from chip companies relating to IP reuse, and what issues are resulting? How can companies overcome these challenges and increase the value of their IP?

A: According to Ron Collett, president and CEO of Numetrics, adding 10 percent of new circuitry to each block in a large design may actually double the total design effort. That's the main dilemma posed by IP reuse, and one that presents a tremendous opportunity for Jasper. We are delivering enabling technology to address IP comprehension, reuse, modification and collaborative coding as we believe the industry has focused a great amount of energy on packaging IP, but very little on solving basic challenges. It is naïve to think of IP as plug-and-play. It's not enough to verify protocols. The block must achieve true interoperability with the rest of the chip's logic. We're empowering designers with the knowledge they need to actually comprehend and integrate IP safely so the reuse paradigm can be leveraged to its maximum potential.

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