Moving 3D ICs into Mainstream Design Flows
Volume production of 3D ICs with through-silicon vias (TSVs) is expected within
a few years. Early adopters of this new technology can expect higher bandwidths,
lower power, increased density and reduced costs. But without “3D aware”
tools and a mature supply chain ecosystem, 3D ICs cannot move into mainstream IC
3D ICs are attractive because they enable an assortment of die, manufactured at
various process nodes, to be stacked. For example, a 28 nanometer high-speed digital
logic die could be stacked with a 130 nanometer analog die. Thanks to such capabilities,
heterogeneous 3D ICs with TSVs are expected to have a broad impact in such areas as
networking, graphics, mobile communications, consumer devices and computing.
MEMS-enabled SoCs Drive Test Innovation
The evolution of the micro-electro-mechanical systems (MEMS) industry is following
a path similar to the maturation of the mixed-signal system-on-chip (SoC) industry.
Demand for MEMS features, especially from the consumer market, is driving the integration
of MEMS functionality into SoCs. The emergence of standard MEMS processes, the integration
of MEMS design and verification functionality into mainstream EDA tools, and the
availability of MEMS intellectual property (IP) will enable SoCs with multiple MEMS
blocks or features.
The emergence of high-volume, low-cost SoC devices that include
multiple MEMS transducers in the feature set present a difficult
challenge for production test. Rather than integrating MEMS test
capability into traditional SoC automatic test equipment (ATE), the
diversity and complexity of physical stimuli required to test MEMS
will result in a pipeline approach to test and a separation of electrical
and MEMS testing. The need to simplify and reduce the cost of
MEMS testing will drive innovation in MEMS design for test. The
key trends driving current SoC testing will also be critical in the
testing of integrated SoC/MEMS devices.