Power Management IC Trends and Cost-effective Testing
Power management ICs (PMICs) are used in electronic
applications or devices to manage the voltage and current.
PMICs can contain battery management, voltage regulation,
charging and digital current to digital current (DC-DC) converters¹
among other functions. In Figure 1, PMICs constitute a large portion
of the "voltage regulator" revenues, and the continued growth in
market size is shown. The growing demand of portable applications,
the volume of which is consumer driven, is a large component of this
growth. As a result, two trends have emerged.
One is for lower cost, simple PMICs, many of which are being
integrated into their host IC's package, thus becoming a system-on-
chip (SoC) (e.g., entry-level, single-chip cellphone ICs with an
integrated PMIC). These devices supply very basic features (many of
the phones are voice only) to emerging cellphone markets.
Figure 1. Analog IC Revenue by Type
Source: Gartner (2010)2
The other trend is to have more complex PMICs (for higher
end stand-alone applications) become part of the chipset of the
application. Examples of this are feature-rich cellphones or mobile
Because cellphones and mobile computing devices are marketed
in consumer markets, lower cost pressures are always present, and,
in fact, include cost-of-test (COT) targets that continually decrease
Another continuing trend pertaining to the functional technology
of PMICs is improved efficiency to extend the battery life of the
mobile appliances the PMICs are used in. In synergy with this, is
lower power consumption of the applications they support.
PMIC Device Overview
The block diagram in Figure 2 shows a PMIC designed to supply
multiple voltages to a complex consumer device (in this case, a
cellphone). A stand-alone PMIC would be very similar, but would
have fewer low-dropout (LDO) outputs and interfaces. The colored
blocks are functions internal to the PMIC device, while the white
blocks are functions interfaced to the outside of the device.
Figure 2. PMIC Block Diagram for a Cellphone
The battery control monitors incoming power sources and
charges the main battery as needed. The voltage reference section
contains the bandgap reference, which is used as a reference voltage
throughout the device. This section is individually trimmed during
test, and accuracy is critical for the remainder of the device to pass
required manufacturing tests. Accuracy is covered further in the next
section. The clock and timing section provides clock distribution
and timing to the digital logic section and determines the device
power-up and power-down sequences. The device has a very specific process to
go through for each of these operations to avoid damage caused by surges or overloads.
The LDO regulator section provides
the different voltages and currents to the different "power domains"
the PMIC supplies. A power domain is an individual supply separate
from the other supplies. In SoC devices, this is very application driven
and could encompass as many as 20 or more domains. The
LDO allows for a diminutive difference in the voltage between the
input and the output (I/O), which allows a much greater range of
input voltages still supplying the correct output voltage. This block
also contains boost (step-up) and buck (step-down) voltage functions
used internally. The liquid crystal display (LCD) driver drives the
phone video display, and the interface section complies with different
interface standards to move video, digital and audio data in and out
of the PMIC. Other functions in this section include the speaker I/O
used to interface the phone's microphone and speaker, the keypad
interface and the motor driver for "silent mode" ringing. Voltage
"level shifters" are used to interface to the subscriber identity module
(i.e., SIM card), and the Universal Serial Bus (USB) data interface is
This article will focus on critical tests and provide an economic perspective.
The bandgap reference test is critical because based on the accuracy
closest to its designed value, the part will fail (or not) because the
other voltages of the LDOs use this reference. This means that a good
part could fail if the reference is trimmed incorrectly, or a marginal
part can be made to pass by having a very accurate trim.
The test carries out several "trims" or voltage measurements and
then a correction, usually by using a digital register (DR) value or by
blowing fuses inside the device connected to resistor trees to correct
the voltage value. Voltage accuracy is critical for this test, not only to
get parts to pass, but also because the production pass yield can be
improved by a more accurate trim. Voltage measurement accuracies
in the 200 ultraviolet (UV) range can have a positive impact on test
economics by improving yield.
The clock and timing tests measure the frequencies of the clocks
internal to the PMIC that supply the timing throughout the IC. The
clocks also feed the digital logic block, which controls much of the
functionality of the device through register control. This influences
the control of the other blocks, including the battery control section
which will determine the best power source and also when to charge
the battery. This is even an important safety issue because most
cellphones use lithium-ion (Li-On) batteries which can overheat and
even explode if charged incorrectly.
LDOs are "mission-critical" test items. Two critical tests include
the testing of:
- Line regulation, where varying input voltages simulating a
battery voltage discharging should produce the same output
- Load regulation, where different current loads (at the output)
simulating various features on the phone being used on-demand
should produce the same output voltage.
Typically, PMICs integrated into SoCs require fewer tests than
standalone PMICs. This is because many of the PMIC functions
are already tested by tests which exercise the SoC functional blocks,
while stand-alone PMICs have no such luxury. Thus, the ratio of the
number of tests from stand-alone PMICs as compared to the SoC-integrated
PMICs can be 5 to 1; however, the stand-alone PMIC has
a much lower average selling price (ASP) than the SoC-integrated
one. As such, a different set of rules must apply to the economics of
Add to this the technical differences between the two, and
different capabilities emerge from an economic perspective of tester
Stand-alone PMIC Tester Requirements
The tester must have the capability to test the PMIC functions shown
in Figure 2, including the digital capability for the logic and registers,
high-precision DC pins for the LDOs and bandgap reference, higher
power DC resources for the power supplies and audio type (1–3
KHz) source and measure capability for the speaker and microphone
functions (Figure 2). Since there is much more testing of PMIC
functions for a lower ASP part, this requires much more parallelism
of test in terms of the functions of individual device (concurrent test)
and much more multi-site parallelism. Concurrent test is the ability
to test separate blocks within the device in parallel. For example, the
design of the device could allow the LDOs to be tested in parallel
with the LCD driver (Figure 2). To maximize this, the tester must
be configured to test as many functional intellectual property (IP)
blocks in parallel as the device design will allow, and at the same
time test on the order of eight to 16 devices in parallel with multi-site
efficiency (MSE) in the 95 percent range. This means additional
devices take on the order of 5 percent additional test time as the
initial device.3 For example, at 95 percent MSE, a single-site test time
of 4 seconds would take 5.2 seconds to test eight devices.
SoC-integrated PMIC Tester Requirements
The tester must have full capabilities to test the PMIC part of the
device listed above and also the SoC part of the device, which
performs the end application. Figure 3 shows a generic example of a
single-chip cellphone which would require:
- Radio frequency (RF) capability for the RF transceiver frontend.
- Analog mixed-signal capability for the baseband analog-to-digital
(A/D) and digital-to-analog (D/A) blocks.
- Voice codec and audio functions.
- Digital capability for the digital logic, digital signal processor
(DSP) and microcontroller unit (MCU) onboard the IC.
Figure 3. SoC-integrated PMIC Block Diagram
Since these devices have a higher ASP, it would appear that there
would be less COT and pricing pressure. However, since this device
contains much more complexity, the capital costs of the tester also
increases, so IP blocks still need to be tested in parallel and there
still needs to be multisite at a high efficiency (95 percent), but the
multi-site numbers are relaxed to the four-to-eight in-parallel range.
Another large part of this relaxing is due to the higher cost of more
complex SoC tester resources (e.g., RF or digital) as compared to
those required for stand-alone PMICs (e.g., DC).
Since tester capital cost adds to the overall COT, there is always
a decision to be made for more parallelism versus tester and handler
capital costs. This would include higher capital costs for a larger
configuration of the tester and, potentially, a higher capital cost for
the handler offset by the faster effective test time of higher density
multisite. Higher multi-site handlers can cost more depending on the
baseline of sites used; for example, if the baseline is derived from the
cost of a one- or four-site handler, then an eight- or 16-site handler
will typically be more expensive.
Automatic test equipment (ATE) manufacturers working with customers
have applied several techniques to address PMIC testing needs.
One technique involves a higher integration of resources. Before
parallelism drove cost pressures, a tester resource board might have
a few "pins" per personal computer (PC) board. Pins are defined
as independently functioning resources that allow each pin to have
different settings (e.g., voltage levels, timing and clocks). A higher
level of integration allows for much more than this. For example,
now 128 individual digital pins per board are available.
Another technique involves the integration of multiple functions
within a pin. For example, it is now possible to have digital pins with
individual clocks, voltage levels, timing and DC capability per board.
Even for more sophisticated resources such as analog and mixed-signal,
the number of resources per board has increased significantly.
Because of the previous two points and the higher integration
of these resources to a lower cost infrastructure of the system for
the simpler stand-alone PMIC devices, the test-head fixture these
boards typically plug into has shrunk significantly. For more complex
integrated PMICs, the larger test-head footprint is still used as needed.
ATE resources are being designed more efficiently to lower
overhead in testing multiple devices and concurrently testing
IP blocks. The net result is a lowered individual test time and an
increased MSE. An example of this includes resources designed with
dual port memories so test data can be uploaded and downloaded
simultaneously while testing the device. The bandgap reference trim
is a good test to do in parallel on multi-site applications because it
requires parallel DC measurements and digital register reads and
writes on a per-device basis. Also, DC tests are done as part of the
digital functional tests which are testing clocks and digital logic.
PMICs continue to be a growing market segment due to many
factors, but the growing demand for portable consumer devices is a
primary driver. Two diverging market segments for PMICs have been
shown; there are some similarities and many differences in testing
and economic requirements. Stand-alone PMICs have very low
ASPs, requiring digital, accurate DC resources and audio capabilities.
They must have a high degree of efficient parallelism both inside
the individual device (concurrent test) and in multisite (eight to 16
sites). The PMICs that are integrated into SoCs must have all the
test capability that stand-alone PMICs have and also the additional
requirements of RF, analog/mixed-signal and higher end digital
capability. Furthermore, they must have a high degree of efficient
concurrent test capability, but usually relaxed numbers of multisite
(four to eight sites), mainly due to the increased capital cost of the
more complex tester resources that are required.
The higher cost of added concurrency and multisite has been offset
by ATE manufacturers through product offerings. These include a
higher integration of tester resources, adding more functionality per
resource and the building of a smaller, lower cost infrastructure for
the tester footprint.
About the Author
Don Blair is a principal consultant in the SoC test group for Verigy in
San Diego, California. Mr. Blair has 25 years experience with HP/
Agilent/Verigy and almost 30 years experience in the semiconductor test
industry. He can be contacted at firstname.lastname@example.org.
1 "Power Management IC". Wikipedia, Available online at: http://en.wikipedia.
2 "Competitive Landscape: Power Management IC Vendors," Gartner (14 May
3 "Multi-Site Efficiency and Throughput" by Joe Kelly, Verigy Ltd.
Available online at: http://www1.verigy.com/cntrprod/groups/public/documents/
file/multi-siteefficiencyoct2008.pdf. Page 1.
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