The Lithography Gap Widens at the 20nm Logic Node: New eBeam Approaches Required to Complete the Design Chain
Aki Fujimura, CEO, D2S Inc.
There is no doubt that 193nm immersion (193i) optical
lithography with multiple patterning and complex eBeam
masks is the default lithographic approach for the 20nm design
chain. Until recently, hopes were pinned on extreme ultraviolet
lithography (EUV) as a long-term solution to be available by the
14nm logic node. Several large semiconductor companies have
made significant investments in EUV, and some systems have been
manufactured for development and prototype applications. But as
more investment and time are needed, particularly for system-on-chip
(SoC) manufacturing, extending 193i is an important agenda
for the industry. Early results demonstrate that complex masks and
multiple patterning using new eBeam technologies will enable 193i
to scale beyond the 20nm logic node to at least the 14nm node.
As optical proximity correction (OPC) extended the life of optical
lithography beyond what was thought possible in the past decade,
new eBeam approaches have the potential to do the same in this
decade by enabling aggressive OPC with realistic mask write times.
Snapshot of the Lithographic Landscape
Although the lithographic landscape has been largely monolithic
until now, with 193i lithography extending far beyond its originally
predicted life span, the challenges presented by 20nm-and-beyond
logic nodes suggest different lithographic solutions for different
applications. Mask cost versus the volume of production may be the
key to the choice of lithographic technology for a given design. The
largest volume designs (dynamic random access memory (DRAM),
microprocessors, high-volume SoCs) will probably use 193i with
multiple patterning, each with complex masks or EUV, when it is
available. Smaller volume designs may find maskless lithography
(ML2) more cost-effective, or the designs might employ a hybrid
approach called complementary eBeam lithography (CEBL). The
one trait all these approaches have in common is their use of eBeam
technology. Below is a snapshot of where these options stand today.
EUV
EUV is high-energy ultraviolet radiation that has a much smaller
wavelength than conventional light sources, and therefore should
be able to provide good resolution and depth-of-focus (DoF)
for advanced process nodes far into the future. Several large
semiconductor companies have made significant investments in
EUV, and some lithography systems have been manufactured for
development and prototype applications. Today, the machines are
both more expensive and slower than existing 193i machines. The
masks are also more expensive and have shorter life spans. Because it
is an expensive solution, EUV will likely be targeted for the highest
volume wafers such as DRAM, microprocessors and very high-volume
SoC devices.
Maskless Lithography
Maskless approaches mostly use eBeam to write directly on wafers
(EBDW). With EBDW, no mask is used for the critical dimension
layers of SoC designs. EBDW is also a very good "drill" for creating
small holes with superior DoF. While great improvements in EBDW
throughput have been made in recent years, improvements need to
continue to keep pace with process technologies. Because funding
for research and development (R&D) of new machines is insufficient
from government grants only, significant funding is required from
potential customers. Since such funding is available only from high-volume
manufacturers, new EBDW development is being targeted
at higher volume designs that would require clusters of EBDW
systems to address the throughput of current EBDW systems. Some
new approaches use parallel guns of conventional eBeam writing
approaches, while others explore new territory with the eBeam being
split between a large number of beamlets which expose the resist in
parallel.
Complementary eBeam Lithography
CEBL is a hybrid approach combining 193i and a high-energy
source such as EBDW or EUV. The idea, discussed broadly by Yan
Borodovsky1 of Intel in early 2010, uses a 193i mask-based approach
to print a regular 1D array of lines and spaces at a single pitch. Then
using EBDW or EUV, the lines are cut into a usable device layout
(sometimes called the cut-mask approach). CEBL significantly
reduces the number of masks needed for both high-volume and low-volume applications. For EBDW, this use model promotes the
strength of eBeam writing, while de-emphasizing the difficult parts
that take longer to perfect, by reducing the data variety and the
required stitching accuracy between "shots."
193i with Complex Masks
From the 130nm node onward, ICs could not be manufactured
without the assistance of resolution enhancement techniques (RETs).
RET includes OPC, which adds "assist" features to shapes on the
mask to "trick" the light into creating a pattern transfer as close
as possible to the intended design. OPC and RET have extended
the life of 248nm and 193nm equipment longer than originally
was thought possible. To meet the demands of 20nm-and-beyond
devices, aggressive OPC techniques such as inverse lithography
techniques (ILTs) and source mask optimization (SMO) have been
adopted. However, the growing use of aggressive OPC has given rise
to unacceptable mask write times as reported in a 2009 Samsung
study2. The latest development in eBeam mask writing to address
this issue is model-based mask data preparation (MB-MDP), with
its ability to generate shot lists with overlapped, variable-shaped
beam (VSB) shots. These overlapped shots create the more complex
and higher resolution mask features required, while enabling fewer
shots—and thus shorter write times—for both EUV and 193i masks.
Figure 1. Complex Assist Features Added by OPC Are Now Sub-100nm,
Presenting New Challenges in Accurately Printing Design Features
Source: IBM
The New Face of an Old Problem: Getting Design Features to Print
Accurately at 20nm and Beyond for Both EUV and 193i
The problem of getting design features to print as desired is an
old one. For more than 10 years, OPC has been used to add subresolution
assist features (SRAFs) to compensate for the optical effects
that prevent small features from printing correctly. As assist features
have reached the sub-100nm scale (Figure 1), a new problem has
emerged: Assist features can no longer be reproduced on the mask
faithfully. Due to the Gaussian blur of the electron beam used to
write masks, a 60nm square feature prints not as a square, but as a
randomly sized circle (Figure 2). At the 28nm logic node, SRAFs are
already sub-100nm; the very features intended to ensure accuracy
now print inaccurately. As the industry ramps up beyond the 20nm
logic node with EUV, this becomes an issue for main features as well.
Intervention is required to correct the under-sizing of smaller features.
Figure 2. A 60nm Square Prints Not as a Square but as a Randomly
Sized Circle Which is Bad News for Manufacturing Margin
Source: D2S
Traditional eBeam mask writing approaches assume a simple
corner-rounding model for mask making which is no longer sufficient
for 20nm wafer lithography. A full simulation of the selected eBeam
shots, followed by both a mask development and etching simulation
and a full aerial simulation of the energy deposited on the wafer, is
the only way to really understand how specified design features will
be transformed in the manufacturing process.
New eBeam Technologies to Support EUV and Extend 193i to 14nm
At the 20nm logic node, 40nm to 60nm features (either as standalone
SRAFs or as decoration on main features) will occur commonly on
precision mask layers. By the time EUV is deployed, feature sizes on
wafers will be 20nm wide; meaning main features on masks will be
80nm wide. Mask engineers increasingly need a quick way to analyze
and explore how sub-100nm shapes will appear on a mask, as well as
a way to correct shapes that do not appear as desired. This capability
is needed for both next-generation R&D and failure analysis of mask
defects and wafer hotspots.
Initially, MB-MDP was developed to address the need to improve
write times for complex masks. However, the same approach can
also address under-sizing of sub-100nm features. Until now, all shots
have been considered to be "full strength" for mask data preparation
purposes. However, adjustable dosage helps to improve mask
critical dimension uniformity (CDU) of sub-100nm features that
would otherwise print smaller than intended. Over-sizing the data
(purposefully drawing larger shapes with the knowledge that they
will write smaller on the mask) can also correct small shapes, but the
dose margin (DM) will be poor, and therefore the design will have
less tolerance for manufacturing variation.
Dose modulation and resizing of selected shots simulated to
produce the correct contour size but with better DM, produces
superior results. But the added flexibility afforded by overlapping
shots in MB-MDP gives the advantages of overdosing without adding
to the mask write times. Because all VSB shots, regardless of size, take
the same amount of time to write, overlapped portions are receiving
the additional eBeam energy for "free" (without any additional
write time). Two shots overlapping produce a 2X dose portion with
an approximately Gaussian tail that provides added energy to the
immediately surrounding neighbors. Thus, the same technique of
overlapping shots that reduce shot count for complex mask shapes
at the same time improves DM and applies mask process correction (MPC)
naturally to the sub-100nm features without adding to the
write times. This coincidence enables MB-MDP to perform MPC
simultaneous with shot count reduction.
Conclusions
The entire design and manufacturing ecosystem is involved in
developing several new technologies simultaneously to address the
widening gap in lithography at 20nm and below. As much as OPC
extended the life of optical lithography beyond what was thought
possible in the past decade, new eBeam approaches have the potential
to do the same in this decade. Because it is a critical element to both
the 193i and EUV paths, new eBeam technologies deserve to be a
top priority for both mask and wafer engineers during this decade.
About the Author
Aki Fujimura is the CEO of D2S Inc., managing company sponsor of the eBeam
Initiative. Prior to D2S, he served as CTO at Cadence Design Systems. Fujimura
returned to Cadence through the acquisition of Simplex Solutions, where he
was president, COO and internal board member. He was a founding member
of Tangent Systems in 1984, which was acquired by Cadence Design Systems
in 1989. Fujimura received his bachelor's and master's degrees in electrical
engineering from MIT. Aki Fujimura can be reached at aki@design2silicon.com.
References
1 Yan Borodovsky, SEMATECH Litho Forum, May 10-12, 2010, New York.
2 Samsung, Byung-Gook Kim, et al, Photomask Japan 2009
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