IP Futures: Predictions for IP Evolution

Bill Martin, Mentor Graphics

IP Past
Engineers have always found ways to help reduce the labor-intensive work in chip design. Long before ASIC and IP businesses were created, engineering teams invented standardized building components to reduce labor costs, minimize variability in critical areas and/or help reduce risks in labor pools with too few qualified personnel.

A perfect example would be an I/O pad design. IC designs will contain many I/O pads that require the same functionality, performance and adherence to latch-up, ESD and process specifications. This requires a skilled physical design expert to layout the pad’s geometries to meet these goals. Rather than developing unique instances for each pad, a common schematic and layout were created to accelerate design and reduce risk. IP Memory blocks and compilers were other key building blocks during this time period and used similar principles.

This was years before the ASIC evolution led by VLSI Technology and LSI Logic. Both companies realized that standard libraries (either gate array or standard cell) would remove much of the complexity and resources required to perform design work. Standard libraries used many similar tools but raised the level of abstraction from transistor to gate level. Another tool, RTL synthesis, allowed designers to write RTL code rather than entering schematics composed of gates. Rather than design 10s of gates per day, now engineers could design 1,000s of gates per day. Block-level IP started to be formed in the early ASIC period and 82xx macros enabled many board level designs to be implemented in single chip ASICs.

IP Present
The level of integration continues as subsystems enter the customer domain, allowing customers to purchase subsystems that incorporate digital, analog (PHY) and small embedded driver SW that were designed and tested as a unit. Subsystems reduce the amount of integration, support and functional issues that customers had when purchasing each piece individually. Subsystems REDUCE risks. It won’t be long before subsystems around specific functionality (i.e. USB, PCI Express, Video, Audio, etc.) emerge. At this point, many of these subsystems are still comprised of individual components, but like Lego Blocks, they are much easier to put together.

IP Future
The above subsystems will eventually be integrated into one block, combining the digital and analog logic into a pre-routed physical file. Reasons for this integration include:

1. The level of integration at 45nm and below will provide ‘free gates’ and the wasted area consumed by this integration will be small. Rather than have the RTL configured and then synthesized and routed into optimized gates, the configuration will be built into the silicon and users will tie or drive signals to specific values for specific configurations. The configurations would be restricted to ‘non x-Lane’ options, allowing IP consumers to define products that could have on the fly configurability. Inactive gates used in one application might be driven active by control signals within the chip. A simple example would be to use a common SERDES with different, “switchable” Digital Front-Ends for PCI Express or SATA or other applications.
   
2. The higher frequencies required by the standard interfaces will require tighter control on the placement of the digital and analog blocks. This will remove one variable that otherwise might prevent subsystems form working. The block will be tuned for a specific process and allow test chips to be supplied to potential IP customers for their evaluation.
3. 
   There will be fewer foundries/processes for which to create physical blocks. In the past, for each foundry and each process, new physical designs were required. This quickly increased the number of physical blocks required to suit each foundry/process combination. With the Common Platform approach, a process and mask set will work across many foundries significantly reducing the number of variations.

Both IP providers and consumers will benefit from this solution. IP providers will create larger integrated blocks that will not require customer tweaking, thus reducing the amount of support requested. IP consumers will get pre-defined blocks that have built in configurability, have proven silicon and reduce risk. Integration of these subsystems will be much easier than integrating the subcomponents.

What happens to IP from the past? All of these will continue to be migrated to future process nodes. Many changes in process, design and market requirements (decreasing supply voltages, rapidly increasing bit-counts and clock-speeds, noise, radiation, temperature, etc.) pose new challenges that require these IP to be updated.

Tell us your vision of how you think IP will morph in the next 5 years?