IP Acquisition & Management

• Access to IP Acquisition & Management services from Silicon-IP.com

IP ROI Calculator

• Mentor Graphics

  The IP ROI Calculator was created to provide a framework that allows users to add their own data and criteria for their Make vs. Buy decision. Functioning as an excel workbook, the calculator has five main sections - Introduction, IP Qualitative, IP make vs. Buy, Product ROI and Sensitivity Analysis.

IP Catalogs

• GSA is pleased to offer complimentary access to IP catalogs from ChipEstimate.com , Design & Reuse and IPSupermarket.com.

GSA Interest Group Survey

• GSA's Interest Groups are driving industry solutions in EDA/Design, IP, Wafer Manufacturing, Packaging and Test. Help us by giving your feedback in these areas.

Suppliers and Service Partners

• Suppliers to the semiconductor industry are eligible for inclusion in the GSA Supplier & Service Partner Profile Directory. To submit your company for inclusion, please complete this survey and submit it to GSA.

2010 GSA Memory Conference Report

• “Bridging Memory and Logic ICs for Better System Performance”
  

  The GSA Memory Conference, held in Taipei on March 16, 2010, ended with great success. The 2010 GSA Memory Conference Report records the key perspectives and insights from the distinguished speakers and the companies they represented at this conference. It also brings together impartial views and comments from the Industrial Economics and Knowledge Center (IEK), the industrial research arm of the Industrial Technology Research Institute (ITRI), a long-term associate to GSA.

Outsourcing IP Market Reports

• GSA is pleased to collaborate with IPnest to offer comprehensive industry reports on various IP. IPnest provides strategic marketing expertise to various IP vendors and market surveys focused on wired Interface IP (PCIe, SATA, USB, DDR, HDMI).

New Patent Law

• LOGIN
  Sunshine Intellectual Property Firm

  PDF, 175 KB

Understanding Fabless IC Technology

• Authors: Jeorge S. Hurtarte, Evert A. Wolsheimer, Lisa M. Tafoya

  Understanding Fabless IC Technology focuses on the differences between the IDM and fabless business model and provides the reader with an overview of how to conduct business in the outsourced semiconductor industry environment as well as discusses technical, cultural and global issues. It also discusses key business topics such as negotiating with outside fabrication companies, choosing the right electronic design tools, protection of intellectual property and business plans, and maintaining quality control.

Building a Better Supply Chain: Successful Collaboration in the Fabless Semiconductor Industry

• Industry Directions and GSA

  A collaborative effort between industry analyst firm Industry Directions, Inc. and GSA, the study demonstrates that while fabless companies are adept at operating in the outsourced model and recognize the importance of the supply chain and how it helps drive competitive advantage, there is significant opportunity for improvement.

GSA Semiconductor Market Report: An Essential Data Resource for Outsourcing Companies

• The Semiconductor Market Report, last updated in May 2007, is an essential historical data resource that encompasses the entire fabless ecosystem. There is no single source or publication of this caliber with the more than 550 pages of easy-to-read charts, graphs and written analysis.

SIP Business Handbook

• This educational document details the business and legal issues associated with identifying, evaluating and licensing SIP.

  PDF, 214 KB

The Sure Path to 40nm Success

• Virage Logic
  Virage Logic

  PDF, 144 KB

Can MIPI and MDDI Really Co-Exist?

• Ashraf K. Takla, Mixel & Timothy Saxe, QuickLogic

  Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

  PDF, 4.55 MB

IP Acquisition Considerations for Fabless IC Companies

• Start-Up Education
  Peter Lee, President & CEO
  Aplus Flash Technology

IP Conference Taiwan
Hsinchu, Taiwan
May 7, 2009

• Strategizing for a healthy IP ecosystem
  CPU System-Level Optimization For Cost Reduction to Fight Down-turn
  Frankwell Lin, President
  Andes Technology Corporation

  PDF, 1.418 MB

• Strategizing for a healthy IP ecosystem
  A New IP Verification Flow Using ESL
  Dr. Alan P. Su
  Global UnichipCorporation

  PDF, 1.243 MB

• Strategizing for a healthy IP ecosystem
  IP Litigation During Economic Hard Times: Are You Ready?
  Paul M. Saraceni, Esq., Chief IP Officer
  RPX Corporation

  PDF, 783 KB

ITAC and GSA Conference
Waterloo, Ontario, CANADA
April 15, 2009

• Semiconductor Industry Will Innovate its Way Out of the Downturn
  Lisa Tafoya, Vice President of Global Research
  Global Semiconductor Alliance

  The semiconductor industry has a rich tradition of managing through dramatic and unforgiving cycles, ranging from years of extraordinary growth, to steep declines. After several unprecedented years of contiguous growth, the industry is now facing a downturn stunning even industry veterans. Semiconductor companies will not go unscathed in this current environment. Start-ups needing additional rounds of funding and do not yet have a product and are not cash-flow positive are the most vulnerable. However, in general, the industry is in a much stronger position to weather this downturn than it was in 2001. The presentation will provide data and analysis supporting the hypothesis that the semiconductor industry will innovate its way out of the downturn, and how great companies will be prepared for next-generation opportunities.

  PDF, 4.35 MB

DesignCon 2009
Santa Clara, CA
February 4, 2009

• EDA Standards Questionnaire
  Herb Reiter, President
  EDA 2 ASIC Consulting, Inc.

  PDF, 146 KB

• Embracing a New Paradigm: EDA Tools and IP as Solutions Enablers LOGIN
  Bill Martin, General Manager, Verification IP Division
  Mentor Graphics

  PDF, 4 MB

• Semiconductor Market Forecast 2009-2010
  Brian Mata, Vice President
  IC Insights

  PDF, 1.47 MB

GSA IP Fraud Protection Webinar
WebEx
October 8, 2008

• IP Fraud Protection LOGIN
  Chris Jensen, Vice President of Marketing, New Momentum
  New Momentum

  PDF, 6.24 MB

GSA Suppliers Expo & Conference
Santa Slara, CA
October 2, 2008

• Panel Discussion
  IP: How to Successfully Use and Integrate IP LOGIN
  Moderator: Bill Martin, General Manager, Verification IP Division, Mentor Graphics
  Mentor Graphics

  Panel
  Dermot Barry, Vice President Consumer Silicon, Silicon & Software Systems Ltd.
  Ron Burns, General Manager, Semiconductor and Systems Solutions, Wipro Technologies
  Thomas Hartung, Vice President Sales & Marketing, X-FAB Group
  Jeff Lewis, Vice President, Marketing and Product Operations, Innovative Silicon Inc.

  The afternoon panel at the 2008 Suppliers Expo discussed how companies can be successful when using 3rd party IP and services to complete their design. The panel highlighted and included findings from the GSA IP Conference held on September 24-25.

  PDF, 1.48 MB

GSA IP Conference: Strategy for a Healthy IP Ecosystem
Santa Clara, CA
September 25, 2008

• Reducing Hidden Costs in the IP Ecosystem: Where?, When?, How? LOGIN
  Raminderpal Singh, Senior Technical Staff Member, Semiconductor Industry Analyst, IBM Corporate Marketing
  IBM Corporate Marketing

  PDF, 1.18 MB

• Keynote Address
  IP in the SoC Era: Truth & Consequences LOGIN
  Ron Collett, President and Chief Executive Officer, Numetrics Management Systems, Inc.
  Numetrics Management Systems, Inc.

  PDF, 1.31 MB

• Do We Need Unified IP Standards? LOGIN
  Dennis Brophy, Vice Chair, Accellera
  Accellera

  PDF, 1.42 MB

• Creating Best Practices From a Silicon Testing Standpoint LOGIN
  Martin Niset, Product and Test Engineering Manager, Virage Logic
  Virage Logic

  PDF, 944 KB

• Panel Discussion
  What Key Issues and Drivers are Considered When Migrating a Design From One Node to the Next? LOGIN
  Moderator: Ron Wilson, Executive Editor, EDN
  EDN

  PDF, 641 KB

• Panel Discussion
  IP Responsibility . . . The Impact of IP Quality on Time-To-Revenue LOGIN
  Moderator: Kurt Wolf, Director, IP Supplier Management Program, TSMC
  TSMC

  PDF, 1.79 MB

• RDR in the IP Space - Design Methods and Their Impact on IP LOGIN
  Lars Liebmann, Distinguished Engineer, IBM Corporation
  IBM Corporation

  PDF, 1.07 MB

• Panel Discussion
  Integration of Foundry and IP Suppliers LOGIN
  Moderator: Dave Bursky, Semiconductor Editor, Chip Design Magazine
  Chip Design Magazine

  PDF, 1.77 MB

• Panel Discussion
  Understanding and Utilizing a Compatible IP Ecosystem LOGIN
  Moderator: Ana M. Hunter, Vice President, Samsung Semiconductor
  Samsung Semiconductor

  PDF, 2.23 MB

• How Do I Ensure That any Software Will Work in My SoC? LOGIN
  Marc Greenberg, Director of Technical Marketing, Denali Software, Inc.
  Denali Software, Inc.

  PDF, 944 KB

• Keynote Address
  Semiconductor Intellectual Property: The Key to a $100 Billion Market LOGIN
  Jordan Selburn, Principal Analyst, Semiconductor Design, iSuppli Corporation
  iSupply Corporation

  PDF, 286 KB

• Challenges, Consumer Demands and Value-Added Solutions - A Design Community Perspective LOGIN
  Ken Tallo, Director of External IP & Virtual Platforms, Intel Corporation
  Intel Corporation

  PDF, 3.13 MB

• Can Foundries Provide Value to Electronics Companies? LOGIN
  Walter Ng, Vice President, Design Enablement Alliances, Chartered Semiconductor Manufacturing Inc.
  Chartered Semiconductor Manufacturing Inc.

  PDF, 2.29 MB

• Reuse is Surging The Why, How and What? LOGIN
  Adam Traidman, Group Marketing Director, Cadence Design Systems, Inc.
  Cadence Design Systems, Inc.

  PDF, 2.91 MB

• Realizing the Benefits of IP Within Your Design Environment LOGIN
  John Chilton, Senior Vice President, Marketing and Corporate Development, Synopsys, Inc.
  Synopsys, Inc.

  PDF, 3.6 MB

• Panel Discussion
  Expanding Decreasing Margins: Facilitating Improved Margins, Lower Cost and Faster Time-To-Market LOGIN
  Moderator: Jordan Selburn, Principal Analyst, Semiconductor Design, iSuppli Corporation
  iSuppli Corporation

  PDF, 641 KB

• Panel Discussion
  Is Silicon Validation of IP Sufficient? LOGIN
  Moderator: Nitin Deo, Group Director, Cadence Design Systems, Inc.
  Cadence Design Systems, Inc.

  PDF, 1.78 MB

• Panel Discussion
  How Does IP Quality, Verification and Reliability Relate to Yield? LOGIN
  Moderator: Ann Steffora-Mutschler, Senior Editor, EDN
  EDN

  PDF, 642 KB

• Using Hard IP Quality Risk Assessment Tool to Measure IP: Two Examples of Case Studies - Hard IP Blocks LOGIN
  David Schwan, Engineering Manager, CAD and Layout, RFMD
  RFMD

  PDF, 642 KB

• Soft IP in Mobile Handsets LOGIN
  Oliver Gunasekara, Vice President, Mobile Business, W & W Communications
  W & W Communications

  PDF, 20.11 MB

• The High Return on Investment for Embedded Non-Volatile Memory LOGIN
  Craig Rawlings, Director of Marketing, Kilopass Technology, Inc.
  Kilopass Technology, Inc.

  PDF, 1.39 MB

• Benchmarking - Making IP an Important Part of Your Business Strategy LOGIN
  Glenn Raskin, Director Program Manager, Qualcomm
  Qualcomm

  PDF, 642 KB

SEMICON China 2008
Shanghai, China
March 18, 2008

• Tools for Reducing the Hidden Costs in the IP Supply Ecosystem LOGIN
  Moderator: Dr. Raminderpal Singh, Senior Technical Staff Member, IBM IPecosystem Technical Lead, GSA
  IBM

  PDF

FSA Semiconductor Leaders Forum
Taipei, Taiwan
November 7, 2007

• Enhancing IP Access For Fabless Companies LOGIN
  Warren East, Chief Executive Officer, ARM
  ARM

  PPT, 9.6 MB

FSA Webcast: Addressing the #1 Bottleneck to IP Fluidity in the Market
June 26, 2007

• Panel Discussion: Addressing the #1 Bottleneck to IP Fluidity in the Market LOGIN
  Moderator: Ron Wilson, EDN Magazine
  EDN Magazine

  PDF

IET & FSA International Semiconductor Forum
Paris, France
May 15, 2007

• Technical Theme: IP and Reuse
  Leveraging Knowledge and Design Reuse is Critical to Success LOGIN
  Gabriele Saucier, CEO, Chairman of the Board, Design and Re-Use
  Design and Re-Use

  PDF, 608 KB

• Keynote Address: Consolidation and the IP Business Model LOGIN
  Mike Muller, CTO, ARM
  ARM

  PDF, 23.2 MB

FSA International Collaboration Series: Low-Power Design
March 31, 2007

• ARM Solutions and Collaborations for Low Power LOGIN
  Felix Fei, ARM
  ARM

  PDF

Understanding the SIP Business Process Presentation

• LOGIN
  Vin Ratford, Nick Popper, Dan Caldwell and Tom Katsioulas
  Industry Baseline Working Group (IBWG)

  Supplement to the SIP Business Handbook

  PDF, 214 KB

The Challenge Of Re-Use

• Kalar Rajendiran Senior Director of Marketing
  eSilicon Corporation

  This white paper will examine the factors involved in the re-use of existing IP and the addition of third-party IP.

  PDF

Supply Chain Issues In The High-Technology Semiconductor Industry

• Sanjiv Chopra
  Oracle Corporation

  Results of the supply chain survey conducted by Oracle & Global Semiconductor Alliance (GSA) Sanjiv Chopra, Oracle Corporation

  PDF

Sofics hebistors:Latch-up Immune on-chip ESD protection for High Voltage processes and applications

• Bart Keppens
  Sofics BVBA

  While High Voltage interfaces are broadly used in many IC applications like motor control, power management and conversion, LCD panel drivers and automotive systems, many IC designers still lack a low leakage, costeffective and latch-up immune ESD protection clamp. This white paper introduces a newly developed protection device and compares it with the traditional approaches, based on measurements on TSMC 0.35um 15V and TSMC 0.25um 40V technology. Within an area of 35.000um², the novel hebistor device with holding voltage above 40V achieves more than 4kV HBM, 200V MM while the leakage and capacitance stay well below typical requirements (<10nA and <250fF). Hebistors form a family of high voltage ESD/EOS/IEC protection clamps which are branded under the Sofics PowerQubic portfolio.

  PDF, 486.959 MB

Eliminating Embedded Non-Volatile Memory IP Risks in SOCs

• Linh Hong
  Kilopass

  With many embedded logic NVM options available, chip developers, foundry IP managers, and reliability managers need to narrow down the list of vendors by evaluating the risk of integrating an NVM IP. In this paper you will learn what to look for to ensure that the NVM IP will not cause headaches when your product goes into volume production.

  PDF, 308 KB

Exploiting Core’s Law: Get “More than Moore” productivity from your ASIC and SOC Design Teams

• LOGIN
  Tensilica

  PDF, 705 KB

Phase-Locked Loops Demystified

• LOGIN
  John Maneatis, Ph.D.; Eskinder Hailu, Ph.D.
  True Circuits

  PDF, 126 KB

Brand Protection

• LOGIN
  Chris Jensen, Vice President of Marketing
  New Momentum

  A white paper about counterfeiting and unauthorized sales of semiconductor Intellectual Property

  PDF, 110 KB

Addressing Design Challenges at 130-Nanometer and Below: The Silicon Readiness Approach

• LOGIN
  Aurangzeb Khan
  Cadence Design Systems

  PDF

The Current State of Semiconductor Intellectual Property (SIP) Licensing White Paper

• Nick Popper, Reporter
  GSA Model License Agreement Working Group

  A document identifying and summarizing common issues encountered in third-party IP negotiations for use by third-party IP integrators.

  PDF