GSA Member Login | March 17, 2010
Intellectual Property (IP)
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Intellectual Property

Statement of Challenges

  • Design complexity continues to grow, while development schedules and resources continue to shrink
  • Quality and integration continue to be issues with increasing reliance on pre-made IP and IP subsystems
  • Choosing a good IP provider is difficult with continual consolidation among IP providers
  • Performing Make vs Buy decisions with IP is difficult

Mission

To address IP industry challenges preventing consumers from success with IP. The IP includes: silicon,embedded software, verification and system level IP.

Objectives

  • Uncover the obstacles preventing IP vendors from successfully selling IP and the obstacles that are preventing IP users from successfully integrating IP
  • Develop tools that enable greater communication and decision making
  • Improve IP usage by applying metrics that align users and sellers on key success indicators (KSIs)

Get Involved

The IP Interest Group is chaired by Warren Savage, CEO, IPextreme.  GSA is actively seeking semiconductor, IP, and other supply chain partners who work with IP to join the interest group. For more information on how to get involved in the IP Interest Group, contact Kristen Pillans at GSA, 972.866.7579 ext. 124 .

Social Media

Join our Social Media groups and stay informed. LinkedIn groups are specific to each GSA Interest Group/Working Group.

LinkedIn     Twitter

GSA Intellectual Property

Events

DesignCon 2010

The IP Interest Group hosted a tutorial regarding the common challenges facing IP reuse and best practices, as well as explained the readily-available resources accessible to companies today.

Introduction to IP Initiatives at the GSA
Warren Savage, President & CEO, IPextreme & GSA IP Working Group Chair

Keynote 1: The Shift of Innovation to the Edges (Presentation Not Available)
Dr. Juan-Antonio Carballa, Semiconductor Venture Capital partner and worldwide Head for IBM's Microelectronics Services team

Delivering Quality FPGA IP
Jason Lawley, Staff Design Engineer Manager, Xilinx

IP Licensing Best Practices
Kurt Wolf, President, SiliconIP

Keynote 2: The Evolving Supply Chain
Phil Casini, VP Marketing, Chip-Start & Managing Director, Advanced Tech Marketing

Top 5 Tips for Evaluating IP Quality
John Koeter, Vice President Marketing, Synopsys

10 Critical Factors in Selecting Memory IP
Farzad Zarrinfar, President, Novelics

Hard IP from Multiple Sources AND Smooth Foundry Tapeouts
Ken Brock, Director of Physical IP Marketing, Virage Logic

Tools

IP ROI Calculator

  • Bill Martin, General Manager, Verification IP Division
    Mentor Graphics

    The IP ROI Calculator was created to provide a framework that allows users to add their own data and criteria for their Make vs. Buy decision. Functioning as an excel workbook, the calculator has five main sections - Introduction, IP Qualitative, IP make vs. Buy, Product ROI and Sensitivity Analysis.

IP Catalogs

IPecosystem Tool Suite

  • GSA is pleased to offer a new suite of productivity tools that enables more efficient communication between IP vendors, IP integrators and foundries for IP interaction, an area critical for design success. The tools create efficiencies and lower risk by reducing the time spent collecting the specific information required to purchase, integrate and utilize IP.

Surveys     Reports     Articles    Presentations    Whitepapers

Market Intelligence

SURVEYS

GSA Interest Group Survey

  • GSA's Interest Groups are driving industry solutions in EDA/Design, IP, Wafer Manufacturing, Packaging and Test. Help us by giving your feedback in these areas.

Suppliers and Service Partners

  • Suppliers to the semiconductor industry are eligible for inclusion in the GSA Supplier & Service Partner Profile Directory. To submit your company for inclusion, please complete this survey and submit it to GSA.

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REPORTS

Outsourcing IP Market Reports

  • GSA is pleased to collaborate with IPnest to offer comprehensive industry reports on various IP. IPnest provides strategic marketing expertise to various IP vendors and market surveys focused on wired Interface IP (PCIe, SATA, USB, DDR, HDMI).

New Patent Law

  • LOGIN
    Sunshine Intellectual Property Firm

    PDF, 175 KB

Understanding Fabless IC Technology

  • Authors: Jeorge S. Hurtarte, Evert A. Wolsheimer, Lisa M. Tafoya

    Understanding Fabless IC Technology focuses on the differences between the IDM and fabless business model and provides the reader with an overview of how to conduct business in the outsourced semiconductor industry environment as well as discusses technical, cultural and global issues. It also discusses key business topics such as negotiating with outside fabrication companies, choosing the right electronic design tools, protection of intellectual property and business plans, and maintaining quality control.

Building a Better Supply Chain: Successful Collaboration in the Fabless Semiconductor Industry

  • Industry Directions and GSA

    A collaborative effort between industry analyst firm Industry Directions, Inc. and GSA, the study demonstrates that while fabless companies are adept at operating in the outsourced model and recognize the importance of the supply chain and how it helps drive competitive advantage, there is significant opportunity for improvement.

GSA Semiconductor Market Report: An Essential Data Resource for Outsourcing Companies

  • The Semiconductor Market Report, last updated in May 2007, is an essential historical data resource that encompasses the entire fabless ecosystem. There is no single source or publication of this caliber with the more than 550 pages of easy-to-read charts, graphs and written analysis.

SIP Business Handbook

  • This educational document details the business and legal issues associated with identifying, evaluating and licensing SIP.

    PDF, 214 KB

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ARTICLES

The Sure Path to 40nm Success

  • Virage Logic
    Virage Logic

    PDF, 144 KB

Can MIPI and MDDI Really Co-Exist?

  • Ashraf K. Takla, Mixel & Timothy Saxe, QuickLogic

    Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

    PDF, 4.55 MB

IP Acquisition Considerations for Fabless IC Companies

  • Start-Up Education
    Peter Lee, President & CEO
    Aplus Flash Technology

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PRESENTATIONS

IP Conference Taiwan
Hsinchu, Taiwan
May 7, 2009

ITAC and GSA Conference
Waterloo, Ontario, CANADA
April 15, 2009

  • Semiconductor Industry Will Innovate its Way Out of the Downturn
    Lisa Tafoya, Vice President of Global Research
    Global Semiconductor Alliance

    The semiconductor industry has a rich tradition of managing through dramatic and unforgiving cycles, ranging from years of extraordinary growth, to steep declines. After several unprecedented years of contiguous growth, the industry is now facing a downturn stunning even industry veterans. Semiconductor companies will not go unscathed in this current environment. Start-ups needing additional rounds of funding and do not yet have a product and are not cash-flow positive are the most vulnerable. However, in general, the industry is in a much stronger position to weather this downturn than it was in 2001. The presentation will provide data and analysis supporting the hypothesis that the semiconductor industry will innovate its way out of the downturn, and how great companies will be prepared for next-generation opportunities.

    PDF, 4.35 MB

DesignCon 2009
Santa Clara, CA
February 4, 2009
  • Embracing a New Paradigm: EDA Tools and IP as Solutions Enablers LOGIN
    Bill Martin, General Manager, Verification IP Division
    Mentor Graphics

    PDF, 4 MB

GSA IP Fraud Protection Webinar
WebEx
October 8, 2008

  • IP Fraud Protection LOGIN
    Chris Jensen, Vice President of Marketing, New Momentum
    New Momentum

    PDF, 6.24 MB

GSA Suppliers Expo & Conference
Santa Slara, CA
October 2, 2008

  • Panel Discussion
    IP: How to Successfully Use and Integrate IP LOGIN
    Moderator: Bill Martin, General Manager, Verification IP Division, Mentor Graphics
    Mentor Graphics

    Panel
    Dermot Barry, Vice President Consumer Silicon, Silicon & Software Systems Ltd.
    Ron Burns, General Manager, Semiconductor and Systems Solutions, Wipro Technologies
    Thomas Hartung, Vice President Sales & Marketing, X-FAB Group
    Jeff Lewis, Vice President, Marketing and Product Operations, Innovative Silicon Inc.

    The afternoon panel at the 2008 Suppliers Expo discussed how companies can be successful when using 3rd party IP and services to complete their design. The panel highlighted and included findings from the GSA IP Conference held on September 24-25.

    PDF, 1.48 MB

GSA IP Conference: Strategy for a Healthy IP Ecosystem
Santa Clara, CA
September 25, 2008

  • Reducing Hidden Costs in the IP Ecosystem: Where?, When?, How? LOGIN
    Raminderpal Singh, Senior Technical Staff Member, Semiconductor Industry Analyst, IBM Corporate Marketing
    IBM Corporate Marketing

    PDF, 1.18 MB
  • Keynote Address
    IP in the SoC Era: Truth & Consequences LOGIN
    Ron Collett, President and Chief Executive Officer, Numetrics Management Systems, Inc.
    Numetrics Management Systems, Inc.

    PDF, 1.31 MB
  • Do We Need Unified IP Standards? LOGIN
    Dennis Brophy, Vice Chair, Accellera
    Accellera

    PDF, 1.42 MB
  • Creating Best Practices From a Silicon Testing Standpoint LOGIN
    Martin Niset, Product and Test Engineering Manager, Virage Logic
    Virage Logic

    PDF, 944 KB
  • Panel Discussion
    What Key Issues and Drivers are Considered When Migrating a Design From One Node to the Next? LOGIN
    Moderator: Ron Wilson, Executive Editor, EDN
    EDN

    PDF, 641 KB
  • Panel Discussion
    IP Responsibility . . . The Impact of IP Quality on Time-To-Revenue LOGIN
    Moderator: Kurt Wolf, Director, IP Supplier Management Program, TSMC
    TSMC

    PDF, 1.79 MB
  • RDR in the IP Space - Design Methods and Their Impact on IP LOGIN
    Lars Liebmann, Distinguished Engineer, IBM Corporation
    IBM Corporation

    PDF, 1.07 MB
  • Panel Discussion
    Integration of Foundry and IP Suppliers LOGIN
    Moderator: Dave Bursky, Semiconductor Editor, Chip Design Magazine
    Chip Design Magazine

    PDF, 1.77 MB
  • Panel Discussion
    Understanding and Utilizing a Compatible IP Ecosystem LOGIN
    Moderator: Ana M. Hunter, Vice President, Samsung Semiconductor
    Samsung Semiconductor

    PDF, 2.23 MB
  • How Do I Ensure That any Software Will Work in My SoC? LOGIN
    Marc Greenberg, Director of Technical Marketing, Denali Software, Inc.
    Denali Software, Inc.

    PDF, 944 KB
  • Keynote Address
    Semiconductor Intellectual Property: The Key to a $100 Billion Market LOGIN
    Jordan Selburn, Principal Analyst, Semiconductor Design, iSuppli Corporation
    iSupply Corporation

    PDF, 286 KB
  • Challenges, Consumer Demands and Value-Added Solutions - A Design Community Perspective LOGIN
    Ken Tallo, Director of External IP & Virtual Platforms, Intel Corporation
    Intel Corporation

    PDF, 3.13 MB
  • Can Foundries Provide Value to Electronics Companies? LOGIN
    Walter Ng, Vice President, Design Enablement Alliances, Chartered Semiconductor Manufacturing Inc.
    Chartered Semiconductor Manufacturing Inc.

    PDF, 2.29 MB
  • Reuse is Surging The Why, How and What? LOGIN
    Adam Traidman, Group Marketing Director, Cadence Design Systems, Inc.
    Cadence Design Systems, Inc.

    PDF, 2.91 MB
  • Realizing the Benefits of IP Within Your Design Environment LOGIN
    John Chilton, Senior Vice President, Marketing and Corporate Development, Synopsys, Inc.
    Synopsys, Inc.

    PDF, 3.6 MB
  • Panel Discussion
    Expanding Decreasing Margins: Facilitating Improved Margins, Lower Cost and Faster Time-To-Market LOGIN
    Moderator: Jordan Selburn, Principal Analyst, Semiconductor Design, iSuppli Corporation
    iSuppli Corporation

    PDF, 641 KB
  • Panel Discussion
    Is Silicon Validation of IP Sufficient? LOGIN
    Moderator: Nitin Deo, Group Director, Cadence Design Systems, Inc.
    Cadence Design Systems, Inc.

    PDF, 1.78 MB
  • Panel Discussion
    How Does IP Quality, Verification and Reliability Relate to Yield? LOGIN
    Moderator: Ann Steffora-Mutschler, Senior Editor, EDN
    EDN

    PDF, 642 KB
  • Using Hard IP Quality Risk Assessment Tool to Measure IP: Two Examples of Case Studies - Hard IP Blocks LOGIN
    David Schwan, Engineering Manager, CAD and Layout, RFMD
    RFMD

    PDF, 642 KB
  • Soft IP in Mobile Handsets LOGIN
    Oliver Gunasekara, Vice President, Mobile Business, W & W Communications
    W & W Communications

    PDF, 20.11 MB
  • The High Return on Investment for Embedded Non-Volatile Memory LOGIN
    Craig Rawlings, Director of Marketing, Kilopass Technology, Inc.
    Kilopass Technology, Inc.

    PDF, 1.39 MB
  • Benchmarking - Making IP an Important Part of Your Business Strategy LOGIN
    Glenn Raskin, Director Program Manager, Qualcomm
    Qualcomm

    PDF, 642 KB

SEMICON China 2008
Shanghai, China
March 18, 2008

  • Tools for Reducing the Hidden Costs in the IP Supply Ecosystem LOGIN
    Moderator: Dr. Raminderpal Singh, Senior Technical Staff Member, IBM IPecosystem Technical Lead, GSA
    IBM

    PDF

FSA Semiconductor Leaders Forum
Taipei, Taiwan
November 7, 2007

  • Enhancing IP Access For Fabless Companies LOGIN
    Warren East, Chief Executive Officer, ARM
    ARM

    PPT, 9.6 MB

FSA Webcast: Addressing the #1 Bottleneck to IP Fluidity in the Market
June 26, 2007

  • Panel Discussion: Addressing the #1 Bottleneck to IP Fluidity in the Market LOGIN
    Moderator: Ron Wilson, EDN Magazine
    EDN Magazine

    PDF

IET & FSA International Semiconductor Forum
Paris, France
May 15, 2007

  • Technical Theme: IP and Reuse
    Leveraging Knowledge and Design Reuse is Critical to Success LOGIN
    Gabriele Saucier, CEO, Chairman of the Board, Design and Re-Use
    Design and Re-Use

    PDF, 608 KB
  • Keynote Address: Consolidation and the IP Business Model LOGIN
    Mike Muller, CTO, ARM
    ARM

    PDF, 23.2 MB

FSA International Collaboration Series: Low-Power Design
March 31, 2007

  • ARM Solutions and Collaborations for Low Power LOGIN
    Felix Fei, ARM
    ARM

    PDF

Understanding the SIP Business Process Presentation

  • LOGIN
    Vin Ratford, Nick Popper, Dan Caldwell and Tom Katsioulas
    Industry Baseline Working Group (IBWG)

    Supplement to the SIP Business Handbook

    PDF, 214 KB

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WHITEPAPERS

Sofics hebistors:Latch-up Immune on-chip ESD protection for High Voltage processes and applications

  • Bart Keppens
    Sofics BVBA

    While High Voltage interfaces are broadly used in many IC applications like motor control, power management and conversion, LCD panel drivers and automotive systems, many IC designers still lack a low leakage, costeffective and latch-up immune ESD protection clamp. This white paper introduces a newly developed protection device and compares it with the traditional approaches, based on measurements on TSMC 0.35um 15V and TSMC 0.25um 40V technology. Within an area of 35.000um², the novel hebistor device with holding voltage above 40V achieves more than 4kV HBM, 200V MM while the leakage and capacitance stay well below typical requirements (<10nA and <250fF). Hebistors form a family of high voltage ESD/EOS/IEC protection clamps which are branded under the Sofics PowerQubic portfolio.

    PDF, 486.959 MB

Eliminating Embedded Non-Volatile Memory IP Risks in SOCs

  • Linh Hong
    Kilopass

    With many embedded logic NVM options available, chip developers, foundry IP managers, and reliability managers need to narrow down the list of vendors by evaluating the risk of integrating an NVM IP. In this paper you will learn what to look for to ensure that the NVM IP will not cause headaches when your product goes into volume production.

    PDF, 308 KB

Exploiting Core’s Law: Get “More than Moore” productivity from your ASIC and SOC Design Teams

  • LOGIN
    Tensilica

    PDF, 705 KB

Phase-Locked Loops Demystified

  • LOGIN
    John Maneatis, Ph.D.; Eskinder Hailu, Ph.D.
    True Circuits

    PDF, 126 KB

Brand Protection

  • LOGIN
    Chris Jensen, Vice President of Marketing
    New Momentum

    A white paper about counterfeiting and unauthorized sales of semiconductor Intellectual Property

    PDF, 110 KB

Addressing Design Challenges at 130-Nanometer and Below: The Silicon Readiness Approach

  • LOGIN
    Aurangzeb Khan
    Cadence Design Systems

    PDF

The Current State of Semiconductor Intellectual Property (SIP) Licensing White Paper

  • Nick Popper, Reporter
    GSA Model License Agreement Working Group

    A document identifying and summarizing common issues encountered in third-party IP negotiations for use by third-party IP integrators.

    PDF

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GSA Intellectual Property Blog

Monday, April 13, 2009

A simple model for first order IP make/buy decisions

Jack Harding and Bill Martin

Option Theory contains many different, complex models concerning financial option pricing (stocks, derivatives, etc) between a seller and a buyer. Initial research was performed in the early 1900’s but did not accelerate until the 1960/70’s and is based upon complex math (differential equations, stochastic calculus, Monte Carlo, etc). Several Nobel Prizes have been awarded on work performed in this area. As stated, the work tries to evaluate pricing based upon an asset’s value, inherent market risks and realistic returns.

Do we need complex analysis to help us determine whether to purchase an IP asset or to internally develop IP? We believe that much of the complexity can be eliminated by analyzing two key attributes. This brief discussion might help resolve your IP purchasing decisions.

A “Make” or “Buy” IP decision can be aided by looking at two attributes and creating a map for all combinations. For two variables, this would be a 2x2 scenario matrix. The attributes to consider would be a differentiated feature and your company’s capabilities.

A differentiated feature allows your product or service to be beneficially unique from other competitors. An example might be a very high speed SERDES design with NO jitter. Another might be ‘universal’ digital controller for PCI Express, USB, Ethernet and SATA all wrapped into one RTL code with ‘on the fly’ configurability by user. To our knowledge, neither product exists. Each company determines how differentiation allows them to compete.

Your company’s capabilities help you determine how to best use your resources. Your company might have specific skills or experiences that can set you apart from your competition. Perhaps it is outstanding marketing, brand recognition, customer service, product development, engineering or operations. Few companies have outstanding logistic management. FedEx built their business on next-day delivery and this capability was used to differentiate FedEx’s service. FedEx can easily apply these capabilities to open new business lines such as Fleet Management, Outsourcing Shipping functions at large catalog companies, etc. It would not make sense for FedEx to expand into non-adjacent services. A simple example might be business process outsourcing. FedEx does not have the skills or experience to be successful in this area. If they wanted to enter this market, they would need to acquire an existing company.

How can this be applied to IP purchases?
To fill in the scenario matrix, let’s use easy questions to help guide us.


Will the IP help differentiate your product in the market? Is there a unique capability or performance that distinguishes you from other products?

If you look at common standards-based IP, the value is that it works on a worldwide defined standard. Connecting to this network (i.e. USB) ensures that your product can communicate with any USB enabled device. A USB connector alone does not differentiate your product in the market.

If however, you did have the “universal” digital controller enabled device mentioned above, your product can easily configure for any available network choosing the highest bandwidth available.

If the answer to the above questions are, “no, this IP would not differentiate my product,” you should immediately purchase IP if it is available. In Figure 1, this would be the bottom row filled with “Buy” recommendations. With a “no” answer, we have eliminated two of the four potential scenarios.

If the IP in question does differentiate your product, then you need to examine your staff’s capabilities. This will determine how to best acquire this IP. Let’s add another question to help resolve another scenario.

Does your staff have the right skills and experience to enable successful development?

If you do not have the right experiences, you would minimize your risks by finding an IP vendor with a successful track record. You might pay a premium for this but the insurance lowers your risks. In the diagram, this is the upper right-hand corner denoted “Carefully Buy”. This purchase is slightly different than the preceding recommendations. In this case, this is a differentiated capability for your product and you might consider methods to ensure exclusivity. If your competitors are able to purchase the same IP, your advantage has a low barrier.

So after two questions, we have resolved three of the four scenarios. For the above three scenarios, a user could use the GSA’s IP ROI Calculator but focus on licensing, royalty, and maintenance costs in regards to overall product costs. A user can look at different purchasing models to determine an appropriate model and price.

The most difficult scenario is when the IP does differentiate your product AND your staff has the skills/experience to develop the IP block. In Figure 1, this is the upper left-hand corner denoted with “Make?”.


To answer this, you will need to examine the opportunity or trade-off costs in how your staff is used. Which activity will provide the highest return to your company? This is complex and has many variables to trade-off. The entire IP ROI calculator can be used to help review which action will have the best return.




What other techniques do you use to analyze available options?

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posted by Bill Martin at 7:17 AM 0 Comments

Monday, March 2, 2009

IP Quality: What are you paying for?

Bill Martin, Mentor Graphics

Quality is an old concept with various definitions and diagnostic tools to help improve quality. During the 1960s, few purchased Japanese cars. Today, most prefer Japanese cars due to their reliability and lower total cost of ownership. If you want to explore quality in depth, look for material written by Deming, Juran, Crosby, etc.

The Basic Definition of Quality
The basic definition of quality is simply meeting your customer’s expectations. Note: this does NOT imply the BEST product. One example to show various levels of quality would be different hotel chains. If you stay at Hilton vs. La Quinta hotel, you have different expectations on price and overall service. Both are great hotels and I have stayed at each. But I have different quality expectations for each hotel. If you pay more money, you expect more amenities. If you receive amenities meeting or exceeding your expectations, you are happy. If you do not, you may complain to the hotel management.

What about IP quality?
Several years ago at an IP industry panel, we discussed ‘standards.’ I created a diagram of five circles surrounding the customer. I labeled these: Specification Compliance, Integration, Quality, Business and Legal. Here are brief descriptions for each.

Specification Compliance:
Does the design or IP block meet the standard’s specification (USB, SATA, Ethernet) and can it pass their SIG testing and plug fest events? Without working in this environment, your product cannot ‘touch’ the network and will provide little value to your end customer. These compliance events are regularly held around the world and final reports are created for each vendor’s tests. IP products that pass these tests should not have functional defects.

Integration:
Can the purchased IP easily fit into the design/tool flow that I use? This is different than Specification Compliance. Are standard formats, languages and scripts used for fast adoption? How much energy will it take my team to be able to use and integrate this into my design? As one software vendor states: how much drag is this IP placing on my development?

Quality:
This is quality of the IP’s bill of materials (BOM). Each IP product contains many different subcomponents to help the customer understand how to use the IP. This might include scripts, application notes, reference manuals, verification tests, etc. Quality needs to be viewed in two dimensions: Are all the pieces available? Is each piece complete and easy to understand?

Business:
These are the pricing terms – up-front licensing, royalty or a hybrid model.

Legal:
Legal issues include indemnities, warranties and other terms specifying what happens in various circumstances between the customer and supplier.

In retrospect, I should have merged the above Integration and Quality definition into Integration. Integration would concern integration with tools, other IP and with your product development team. Quality would be the summation of: Specification Compliance, Integration, Business and Legal aspects. The ‘whole enchilada’ needs to meet customers’ expectations to be successful.

When purchasing IP, make sure that you ask questions for each of these areas. GSA has some tools to help you perform due diligence. Ensure that you have the right expectations before you sign a contract otherwise: Caveat emptor.

Post your comments on your definition of quality.

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posted by Bill Martin at 10:20 AM 0 Comments

Monday, February 23, 2009

A Probability Formula for IP Integration

Bill Martin, Mentor Graphics

Years ago, I worked for Bob Payne CTO at VLSI Technology. Bob was great to work for and had many bright ideas concerning ASIC design. One of Bob’s ideas concerned the probability of individual components to the overall project’s probability. You can think of this as ICs being soldered to a PCB or pieces of IP integrated into an IC (SoC, ASSP, FPGA, etc.).

We are not talking about complex Statistics and Probability formulas, but a simple math concept used by many to help calculate overall product costs as well as managing piece part inventories.

How does it work?
To make it work, take the probabilities of each component in your design and multiple them together to determine the end product’s probability of working. This will be the maximum probability since it assumes that top-level integration of these components is perfect in the final product.

Simple example: A product consists of 5 individual components that have probabilities of 80%, 92%, 98%, 99% and 100%. These probabilities were derived from previous usage and estimated for blocks that were modified or never used.

In this case, the overall probability of the end product working is:

71.4% = 80% X 92% X 98% X 99% X 100%

You might ask: how can I apply this to my own situation?

First, by understanding the risk of each component, you can put additional focus on the riskier blocks. In the above case, the block with 80% should be the highest priority of focus. Maybe additional people, different skills, more verification, more/other EDA tools or a different IP supplier might be worthwhile investments. If the 80% block were raised to 90%, the probability of product success would be raised to 80.3%, nearly ~9% higher.

Second, once you have successfully used blocks, you have gained better insight into these blocks. The blocks might be developed internally or purchased, it does not matter. What matters is the probability of each block’s success. Should you reuse these IP, invest more time/energy on them to raise their probabilities or find other alternatives? There are times when any of these actions are appropriate.

Third, some areas of the design might not be well established. The market itself may not have clearly defined a standard. For these situations, if you cannot improve the probabilities of each component, you might as well start planning for several respins OR design your solution so that high-risk elements have minimal impact on your solution.

Some ideas to investigate include: can the high-risk portions be in a separate, self-contained design/chip? Can you enable easy changes to high-risk blocks after silicon (i.e. either software programmable OR placing spare gates near this logic)? Software is the easiest and cheapest for retrofits. Spare gates can help minimize changes to a few mask layers that are used late in the fabrication cycle, allowing you to quickly change logic and ramp up volume production. Either method can help reduce the cost of a respin and minimize your product’s delayed market entry. In most consumer markets, any delay can be very costly regarding sales revenue: possibly a company killer.

Fourth, for any purchased IP, have you considered how you alter the risk profile by modifying that IP block? Is it better to perform modifications external to the purchased IP or should you contact the IP supplier for their assessment?

Fifth, it also shows that reducing the number of components in your design does impact the probability of success as well as the cost. Rather than purchasing independent IP and integrating them, you might consider purchasing a subsystem that has already been integrated and fully tested.

Ron Collett has presented various data points regarding how teams have reduced risk. Figure 1 shows that increasing reuse can help reduce risks in your development.

Figure 1
















What other suggestions do you have on reducing development risk?

posted by Bill Martin at 9:55 AM 1 Comments

Thursday, February 12, 2009

IP Tools: Do any exist to help us?

Bill Martin, Mentor Graphics

If you would have asked me a year ago, few tools or companies were focused on IP quality, reuse and integration. Many managers and engineers complain in the press and at various conferences that problems do exist. If you worked in the IP arena (for example, a supplier or consumer), you had first-hand knowledge of quality and integration issues. There are existing tools from Mentor Graphics (HDL Designer Series), Synopsys (CoreBuilder?), Cadence (ChipEstimate) and Design & Reuse (IP Reuse Station).

In the last six to nine months, I have seen more ‘point’ tools in the press that attack specific issues related to IP. These are not ‘Ron Popeil/Veg-O-Matic-like’ tools (that “does everything to the low cost of $19.95 with lots of extras given away for free”), but at least some point tools are being developed. You might explore the following companies for additional point tool solutions:

Atrenta http://www.atrenta.com/
Fenix Design Automation http://www.fenix-da.com/
NXP/IP Extreme QCore http://www.ip-extreme.com/
Satin IP http://www.satin-ip.com/

I am sure that other companies exist or will be started. Clever people are listening to the IP issues and they are determining how to provide a solution that creates value for all concerned.

If your company has other IP-related tools, please post your company’s name and product below. I am sure many potential customers would like to see what is available.

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posted by Bill Martin at 12:27 PM 2 Comments

Wednesday, February 4, 2009

Altered States: To Change or Not to Change?

Bill Martin, Mentor Graphics

Most people purchase a product and never think about modifying their recent purchase to perform additional functions. If we have issues with these products, we go to the manufacturer or a skilled service provider to fix or replace them, because we know the price of product ‘tinkering’ equals voided warranties and support.

Motive: when it comes to purchased IP, engineers feel they can always improve “off-the-shelf” purchases. The logic says the original designer did not fully understand my specific need, so by adding ‘minor’ tweaks it will enhance the product’s usability. Or will it and at what cost?

Then why do we have different expectations with purchased IP?
Opportunity and Means: Engineers have the opportunity, and means are available to them. Soft IP (RTL) is provided via source code which offers up the opportunity to reconfigure IP. Many engineers can write and understand Verilog or VHDL, providing the means.

So what’s the problem?
Once a modification, however trivial, is implemented on the IP, the original value and purpose created by the IP vendor has been negated. For years, Numetrics has collected various data concerning IC design and the impact of reuse. Figure 1 shows a block that was altered by 25% and the impact on its value. In this case, 25% change reduced the effort saved by 50%. Are the alterations worth the cost?
















Figure 1

The verification, validation and compliance work must be re-done to maintain the original value; very similar to restoring an old car back to its original condition. Few people consider restoration due to the amount of money and work required. The same thoughts should be applied when contemplating IP changes. For IP, the industry does not understand how the IP design team constructed their product or the standard (i.e. USB) specification. At least when re-storing or re-tuning cars, you can buy a complete manual with hundreds/thousands of pages on how the car was constructed with complete BOM and specified parts. Over time, this documentation should become a standard offering available for each IP.

How to avoid domino effects?
In my career, I have had teams that quickly implemented a bug workaround believing that they had complete knowledge of the IP’s interactions. While this might have fixed a specific customer’s issue, it created other issues for other customers’ applications. And this is from the original design team. If they could not understand all the interactions, how could a designer with little history with this IP be able to perform surgery?

I have also had teams that quickly thought of a solution but wanted to run full regression tests to ensure that a small change in one area of the design did not cause issues in other areas. These teams understood that given the IP’s complexity and Murphy’s Law, they were human and could easily introduce bugs.

With the growing complexity of IP, I prefer the latter team’s approach. Determine a solution and re-test it with your regression and silicon validation suites to ensure no unexpected bugs are introduced. The latter approach helps improve IP quality.

Each of us wants to add our own value to a project, but maybe the value we add is by NOT touching an IP block that was purchased. If changes are required, go to the original design team and get a quote from them. In the long run, this will be cheaper and faster.

What are your thoughts on altering IP?

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posted by Bill Martin at 11:47 AM 0 Comments

IP Futures: Predictions for IP Evolution

Bill Martin, Mentor Graphics

IP Past
Engineers have always found ways to help reduce the labor-intensive work in chip design. Long before ASIC and IP businesses were created, engineering teams invented standardized building components to reduce labor costs, minimize variability in critical areas and/or help reduce risks in labor pools with too few qualified personnel.

A perfect example would be an I/O pad design. IC designs will contain many I/O pads that require the same functionality, performance and adherence to latch-up, ESD and process specifications. This requires a skilled physical design expert to layout the pad’s geometries to meet these goals. Rather than developing unique instances for each pad, a common schematic and layout were created to accelerate design and reduce risk. IP Memory blocks and compilers were other key building blocks during this time period and used similar principles.

This was years before the ASIC evolution led by VLSI Technology and LSI Logic. Both companies realized that standard libraries (either gate array or standard cell) would remove much of the complexity and resources required to perform design work. Standard libraries used many similar tools but raised the level of abstraction from transistor to gate level. Another tool, RTL synthesis, allowed designers to write RTL code rather than entering schematics composed of gates. Rather than design 10s of gates per day, now engineers could design 1,000s of gates per day. Block-level IP started to be formed in the early ASIC period and 82xx macros enabled many board level designs to be implemented in single chip ASICs.

IP Present
The level of integration continues as subsystems enter the customer domain, allowing customers to purchase subsystems that incorporate digital, analog (PHY) and small embedded driver SW that were designed and tested as a unit. Subsystems reduce the amount of integration, support and functional issues that customers had when purchasing each piece individually. Subsystems REDUCE risks. It won’t be long before subsystems around specific functionality (i.e. USB, PCI Express, Video, Audio, etc.) emerge. At this point, many of these subsystems are still comprised of individual components, but like Lego Blocks, they are much easier to put together.

IP Future
The above subsystems will eventually be integrated into one block, combining the digital and analog logic into a pre-routed physical file. Reasons for this integration include:
  1. The level of integration at 45nm and below will provide ‘free gates’ and the wasted area consumed by this integration will be small. Rather than have the RTL configured and then synthesized and routed into optimized gates, the configuration will be built into the silicon and users will tie or drive signals to specific values for specific configurations. The configurations would be restricted to ‘non x-Lane’ options, allowing IP consumers to define products that could have on the fly configurability. Inactive gates used in one application might be driven active by control signals within the chip. A simple example would be to use a common SERDES with different, “switchable” Digital Front-Ends for PCI Express or SATA or other applications.
  2. The higher frequencies required by the standard interfaces will require tighter control on the placement of the digital and analog blocks. This will remove one variable that otherwise might prevent subsystems form working. The block will be tuned for a specific process and allow test chips to be supplied to potential IP customers for their evaluation.

  3. There will be fewer foundries/processes for which to create physical blocks. In the past, for each foundry and each process, new physical designs were required. This quickly increased the number of physical blocks required to suit each foundry/process combination. With the Common Platform approach, a process and mask set will work across many foundries significantly reducing the number of variations.


Both IP providers and consumers will benefit from this solution. IP providers will create larger integrated blocks that will not require customer tweaking, thus reducing the amount of support requested. IP consumers will get pre-defined blocks that have built in configurability, have proven silicon and reduce risk. Integration of these subsystems will be much easier than integrating the subcomponents.

What happens to IP from the past? All of these will continue to be migrated to future process nodes. Many changes in process, design and market requirements (decreasing supply voltages, rapidly increasing bit-counts and clock-speeds, noise, radiation, temperature, etc.) pose new challenges that require these IP to be updated.

Tell us your vision of how you think IP will morph in the next 5 years?

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posted by Bill Martin at 11:40 AM 0 Comments

GSA Ecosystem Company Index

GSA is pleased to bring you the GSA Ecosystem Company Index. In an effort to provide the industry with timely information, the GSA Ecosystem Company Indexes provide the supply chain with a listing of companies.

Only Intellectual Property companies are listed on this page. Go to the main GSA Ecosystem Company Index page for the full list.

As a complimentary feature on the GSA site, we encourage all semiconductor supply chain professionals to add their listing. Go to the Company Index Form to create or update your existing record.

Aspex Semiconductor Ltd
Aspex House 44/45 Oxford Street
44/45 Oxford Street
High Wycombe , Buckinghamshire HP11 2DJ
UK
http://www.aspex-semi.com

B-DeltaCom
P.O.B 3590
Caesarea , N/A 38900
Israel

BDTI
2101 Webster St., Suite 1450
Oakland , CA 94612
USA
www.BDTI.com

Cambridge Analog Technologies
54 Middlesex Turnpike, Suite 1250
Bedford , MA 01730
USA
www.cambridgeanalog.com

Capital Ideas
3931 Jefferson Ave
Woodside , CA 94062
USA
www.capital-ideas.com

ChipStart LLC
228 Hamilton Ave.
3rd Floor
Palo Alto , CA 94301
USA
www.chip-start.com

eBeam Initiative
4040 Moorpark Avenue #250
San Jose , CA 95117
USA
www.ebeam.org

eInfochips
1230 Midas Way, Suite# 200
Sunnyvale , California 94085
USA
http://www.einfochips.com

Faraday Technology
490 DeGuigne Drive
Sunnyvale , CA 94085
USA
www.faraday-tech.com

Helion Technology Limited
Ash House, Breckenwood Road
Fulbourn
Cambridge , Cambs CB21 5DQ
UK
www.heliontech.com

IDENT Technology AG
Argelsrieder Feld 5
Wessling , Bavaria 82234
Germany
www.ident-technology.com

IN2FAB Technology Ltd.
1 Silver End
Olney , Buckinghamshire MK46 4AL
UK
www.in2fab.com

Infotech Enterprises Ltd.,
Plot No.11 Software Units Layout Infocity, Madhapur
Hyderabad , Andhra Pradesh 500 081
India
http://www.infotech-enterprises.com

Innovative Logic Inc.
3940 Freedom Circle
Santa Clara , CA 95054
USA
www.inno-logic.com

IP Cores, Inc.
3731 Middlefield Rd
Palo Alto , CA 94303
USA
http://www.ipcores.com

IPextreme
54 North Central Avenue
Suite 204
Campbell , CA 95008
USA
www.ip-extreme.com

Key ASIC
3900 Freedom Circle Suite 101
Santa Clara , CA 95054
USA
www.keyasic.com

MIPS Technologies, Inc.
955 East Arques Avenue
Sunnyvale , California 94085-4521
U.S.A.
www.mips.com

Moortec Semiconductor Ltd
Tamerton Road
Roborough
Plymouth , Devon PL6 7BQ
UK
http://www.moortec.com/

Moscad Design & Automation, Sarl
Chemin des Curtils
Le Vaud , Vaud CH-1261
Switzerland
www.moscad-da.com

MoSys, Inc.
755 N. Mathilda Ave.
Sunnyvale , CA 94085
USA
www.mosys.com

Novocell Semiconductor Inc
3182 Innovation Way, Suite 201
Hermitage , PA 16148
USA
www.novocellsemi.com

nSys Design Systems
35463 Dumbarton Ct
Newark , CA 94560
USA
www.nsysinc.com

Perfectus Technology
Santa Clara , California 95054
USA
www.perfectus.com

RFIC Solutions Inc.
105, Serra Way, #146
Milpitas , California CA - 95035
USA
www.rficsolutions.com

Sidense
84 Hines Road, Suite 260
Ottawa , Ontario K2K 3G3
Canada
www.sidense.com

Silicon & Software Systems
South County Business Park
Leopardstown
Dublin , Co. Dublin 01
Ireland
www.s3group.com

Silicon-IP, Inc.
306 Solana Dr Suite C
Los Altos , CA 94022
USA
www.silicon-ip.com

Sofics BVBA
Brugse Baan, 188a
Gistel , not applicable 8470
Belgium
www.sofics.com

Sonics
890 N. McCarthy Blvd
Suite 200
Milpitas , CA 95035
USA
www.sonicsinc.com

Success Recruitment Group
11 The Enterprise Centre
Coxbridge Business Park
Farnham , Surrey GU10 5EH
United Kingdom
http://www.successrecruitmentgroup.com/

UbiMOS Technologies Inc.
3907 North First Street
San Jose , CA 95134
USA
www.ubimos.com

Virage Logic
47100 Bayside Parkway
Fremont , CA 94538
United States of America
www.viragelogic.com

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