MEMBERSHIP BENEFITS

Collectively Address Industry Challenges Through Subcommittees

Subcommittee participation is strongly encouraged. Members can make a difference by actively participating in one or more of GSA subcommittees listed that address industry issues. Participation is important to ensure that the subcommittees bring valuable insight and results to our members. These efforts reduce the barriers to conducting business effectively and aid our members in their success.

Some of the initiatives resulting from GSA subcommittee work include:

Mixed-Signal/RF PDK Checklist - The Mixed-Signal/RF PDK Checklist describes simulation models, technology files, design rule files and parameterized cell generators used to design today's complex mixed-signal and RF ICs. Checklists have been integrated into development workflows and are being delivered with new MS/RF PDKs by member foundries and PDK development service providers.

Mixed-Signal/RF SPICE Model Checklist - The Mixed-Signal/RF SPICE Model Checklist, developed by the Mixed-Signal/RF Subcommittee’s Model Working Group, provides fabless mixed-signal/RF designers using foundry SPICE models with consistent data to make foundry process and IC design decisions. The Checklist streamlines the MS/RF SPICE model extraction and distribution process throughout the semiconductor supply chain including foundry, fabless, EDA, IP and design service providers.

IPecosystem (IPe) Tool Suite - The Suite of tools will create efficiencies and lower risk by reducing the time spent collecting the general information required to purchase, integrate and utilize IP. The goal is to provide companies purchasing IP with a more efficient means of integrating and utilizing IP at various intervals – from pre-purchase, licensing, design and manufacturing.

• Hard IP Quality Risk Assessment Tool - enables companies to collect important information about an IP vendor, its design methodology and the IP under evaluation to enable risk assessment across seven criteria/ categories: IP design, integration, verification, process technology, product documentation, reliability and test. Dr. Raminderpal Singh, Systems and Technology Group, IBM, is the technical lead for this project and has championed the development of the Hard IP Quality Risk Assessment Tool to benefit the IP vendor, integrator/evaluator and foundries involved in system-on-chip design.

Semiconductor IP Handbook - GSA's IP Subcommittee’s Industry Baseline Working Group has developed a handbook on Understanding the SIP Business Process, which includes an overview of the SIP industry, information on SIP-related products, evaluating business models, and licensing SIP products.

• Understanding The Semiconductor Intellectual Property (SIP) Business Process: Finding, Evaluating And Licensing Commercial SIP (Adobe PDF File, 214KB)
• Understanding the SiP Business Process (Adobe PDF File, 590KB)

IP Licensing White Paper - A document identifying and summarizing common issues encountered in third-party IP negotiations for use by third-party IP integrators. This white paper complements the Semiconductor IP Handbook and Users Guide.

For more information, please contact Donna Hoye at 1.888.322.5195, ext 134 or dhoye@fsa.org.