GSA Business Tools
The Suite of tools will create efficiencies and lower risk by reducing the time spent collecting the general information required to purchase, integrate and utilize IP. The goal is to provide companies purchasing IP with a more efficient means of integrating and utilizing IP at various intervals – from pre-purchase, licensing, design and manufacturing. The first of these tools is the GSA Hard IP Quality Risk Assessment Tool, which GSA offers to the semiconductor industry to support the assessment of 3rd party IP.
The GSA's IP Subcommittee’s Industry Baseline Working Group has developed a handbook on Understanding the SIP Business Process, which includes an overview of the SIP industry, information on SIP-related products, evaluating business models, and licensing SIP products.
GSA offers this resource for members to easily identify market saturation levels – helping to analyze growth potential within the different markets and see which companies are competing in what areas. Over 1,200 fabless companies and IDMs are listed under six major end-market application categories, as well as two additional levels of more defined sub-categories.
This four page Process Checklist, developed by the
Process Control Monitoring (PCM)/Process Checklist Working Group,
reflects the key attributes of an AMS/RF foundry process offering and provides standard definitions for quantitative and qualitative metrics that can be used for classification and as figures of merit in selecting an appropriate process and process options for a specific design application.
The Mixed-Signal/RF SPICE Model Checklist, developed by the Mixed-Signal/RF Subcommittee’s Model Working Group, provides fabless mixed-signal/RF designers using foundry SPICE models with consistent data to make foundry process and IC design decisions. The Checklist streamlines the MS/RF SPICE model extraction and distribution process throughout the semiconductor
supply chain including foundry, fabless, EDA, IP and design service providers.
The Mixed-Signal/RF PDK Checklist describes simulation models, technology files, design rule files and parameterized cell generators used to design today's complex mixed-signal and RF ICs. Checklists have been integrated into development workflows and are being delivered with new MS/RF PDKs by member foundries and PDK development service providers.
The GSA/JEDEC JC-14.2 Foundry Process Qualification Guideline, jointly developed by GSA and JEDEC, describes a minimum set of requirements to qualify a new semiconductor wafer process. The document facilitates communication between foundry and customer and speeds up the qualification process through better alignment of expectation s and standardization of deliverables where feasible.
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