Semiconductor IP providers are a critical aspect of the semiconductor supply chain. To date, GSA has created two tools in what will become a full suite of productivity tools that will enable more efficient communication between IP vendors, IP integrators/evaluators and foundries for IP interaction, an area critical for design success. The tools create efficiencies and lower risk by reducing the time spent collecting the general information required to purchase, integrate and utilize IP. The goal is to provide companies purchasing IP with a more efficient means of integrating and utilizing IP at various intervals – from pre-purchase, licensing, design and manufacturing.
The Tools are conveniently packaged in one application to provide IP vendors and integrators/enablers the most efficient and effective method of evaluating IP. Version 4.003 includes Hard IP Quality and Hard IP Licensing.
- The first tool in the suite, the GSA Hard IP Quality Risk Assessment Tool, officially released in December 2006, enables companies to collect important information about an IP vendor, its design methodology and the IP under evaluation to enable risk assessment across seven criteria/categories: IP design, integration, verification, process technology, product documentation, reliability and test. Dr. Raminderpal Singh, Systems and Technology Group, IBM, is the technical lead for this project, which led to the development of the GSA Hard IP Quality Risk Assessment Tool benefiting the IP vendor, integrator and foundries involved in SOC design.
- GSA introduced the second tool, Hard IP Licensing Risk Assessment, in February 2008. This tool focuses on third-party IP licensing to aid in the negotiation process. It leverages the programming and format of the Hard IP Quality Risk Assessment Tool with a set of standard questions addressing the intangible aspects of IP licensing. This makes the time spent collecting information more efficient and decreases the weeks spent on data collection. The questions were developed around categories for the vendor to communicate the abstract answers at critical junctures for negotiation.
- This tool
will include a series of questions for the foundry to communicate the abstract answers at critical junctures for technology information exchange with semiconductor customers.
Visit www.gsaglobal.org/committees/ip for more information or to participate in the Technology Tool development.
- - This tool will focus a series of questions around communication between the IP vendor, integrator and foundry to ensure the chip will manufacture at yield in a timely manner at the lowest possible cost.
The tools are a result of a collaborative effort from GSA members and is seeking additional participation. Visit www.gsaglobal.org/committees/ip for more information or to participate in the IPe Tool Suite development. Dr. Raminderpal Singh, Systems and Technology Group, IBM, is the technical lead for the IPe Initiative.
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