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GSA/SOI Consortium SoC Design Market Survey

Mobile Internet Devices (MIDs) are expected to grow at an unprecedented rate over the next 10 years, resulting in a demand the semiconductor industry has never seen before. According to Morgan Stanley, this growth indicates a potential volume of 10 billion units in this market by 2020.

To prepare for this demand, SOI Consortium and GSA have partnered to help define the technology requirements for MIDs based on information surveyed across major semiconductor companies. By completing this survey, companies will help GSA and SOI Consortium analyze and present relevant insightful information on technology characteristics, supply-chain readiness and affordability of the silicon technology.

Personal Information

First Name

Last Name

Title

Company

Phone

Survey

1. Are you designing, developing, specifying, or involved in an SoC, ASSP or IP development program?

	Yes
	No

2. In which geographical region is your primary workplace?

	Australia / New Zealand		Korea
	Canada		Middle East
	China		Southeast Asia (Malaysia, Singapore, Thailand, Vietnam)
	Europe		Taiwan
	India		United States
	Japan		Other

3. What processor core is your most likely choice for this market?

	ARM 11
	Atom
	Cortex
	PowerPC
	Other

4. What system clock or processor core performance level is required for your primary application?

	≤1.0 GHz
	1.0 to 1.5 GHz
	1.5 to 2.0 GHz
	2.0 to 2.5 GHz
	≥2.5 GHz

What is the timeframe for prototypes and production for your selection?

3Q 2010	1Q 2011	1Q 2012
4Q 2010	2Q 2011	2Q 2012
	3Q 2011	3Q 2012
	4Q 2011	4Q 2012
Unknown

5. What is the most important criteria in choosing an implementation technology (process node, such as 45nm, 28nm, etc. and process technology, such as bulk CMOS, SOI, etc.) for your design?

	Power consumption		Foundry selection: capacity, capability, service and support
	Performance		IP availability
	Chip cost		High voltage requirement
	Total solution or bill of materials cost		High temperature requirement
	Integration density or size (ability to include on-chip DRAM, NVM, RF, etc.)		Radiation robustness
	Other

6. When do you plan to tape-out your first design in the 20/22-nm technology node?

	1H2012
	2H2012
	1H2013
	2H2013
	No plans at this time
	May not need to use 20/22 nm node for our products

7. Which aspect of Moore's Law scaling are you most concerned about as you move to a new technology or technology node? Please select your top priority.

	Net cost reduction per transistor
	Net cost reduction per memory bit
	Total power per transistor (leakage and active power)
	System performance improvement
	Size, weight or density improvement, even if higher unit cost

8. Are you currently using embedded DRAM in your SoC?

	Yes
	No, but would like to if available and cost-effective
	No, not needed

9. Which types of design components would you like to use on your next SoC? (click all that apply)

	Digital logic
	SRAM
	Analog and mixed signal
	SERDES
	High voltage (above 3.3VDC)
	MEMS
	RF transceivers (muxes)
	Photonics (transceivers and sensors)

10. Do you use the same digital/mixed signal SoC for your low-end and high-end designs?

	Yes
	No

11. What is the total power dissipation budget for your typical and current SoC design in Watts?

	≤0.5W
	0.5W - 1W
	1W - 5W
	5W - 10W
	10W - 30W
	>30W

12. What percentage of power savings is required for an equivalent circuit or function in your next design compared to your previous design?

	10%
	20%
	30%
	40%
	>40%

13. What design engagement model do you primarily use?

	IDM using in-house foundry and internally developed processor and memory IP
	IDM using in-house foundry and external processor and memory IP
	ASIC, using external supplier to manage IP acquisition and integration
	COT flow using 3rd party foundry service and external processor and memory IP
	FPGA design

14. What is your current, typical or actual design cycle time from design start to tape out?

	<6 months
	6 - 9 months
	9 - 12 months
	12 - 15 months
	>15 months

15. Have you ever participated in, supported or manufactured a chip or IP block design on SOI?

	Yes - In production now
	Yes - Prototypes only
	No - But interested and may consider in the future
	No - Not interested

16. Which key consideration would trigger your decision for SOI for your next design? (select one)

	Best performance
	Lowest power
	Highest density and highest performance eDRAM
	Highest yield and lowest SER for high density SRAM
	Lowest system cost implementation
	Smallest die size
	Ability to integrate digital and high voltage components on same die
	Ability to integrate digital and photonic components on same die
	Ability to integrate digital and RF components on same die
	Ability to integrate digital and MEMS components on same die

17. What are the inhibitors/barriers that would keep you from adopting SOI? Please select all that apply.

Cost	Perceived schedule risk	Performance/power
Difficult to design	Lack of IP availability	Foundry support
Undecided

18. When do you intend to use 3D packaging technology using TSVs?

	a. Doing it now
	b. Will start in 6 months
	c. Will start in 12 months
	d. No plans. I do not believe 3D packaging will show a positive cost/benefit for my specific application
	e. No plans. Reason:

19. If you intend to use/explore 3D packaging, what is the primary driving factor for this:

	a. I need to reduce the area my design requires and 3D enables a smaller footprint
	b. I need to gain performance advantages enabled by 3D
	c. I gain additional power savings since many of the interconnects are TSV-enabled rather than going externally off the die through typical bonding wire/leads/PCB interconnect.
	d. I reduce the overall inventory costs since many packages are condensed into one
	e. I expect savings from all reasons a-d
	f. Other:

20. If you do intend to use 3D packaging, you:

	a. Expect the main silicon to be CMOS/TSV structures. Other silicon die can be any type (CMOS, SOI, etc) and this will not require TSV support since they will be flipped bonding
	b. Expect the main silicon and other silicon die to all be TSV capable so I can stack multiple die on each other
	c. Initially I expect option a. but long-term I need option b.

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GSA/SOI Consortium SoC Design Market Survey

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