High-Performance, Cost-Effective Heterogeneous 3D FPGA Architectures
February 03, 2012
Brown University
ABSTRACT In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a novel design partitioning methodology that maps the heterogeneous computational resources of an FPGA into a number of die such that the total die area is minimized and the FPGA performance is maximized.

Advances in 3D-IC Testing
February 03, 2012
EE Times Asia
Three-dimensional integrated circuit (3D-IC) systems has the potential to provide significant improvements in performance, power, functional density, and form factor over other packaging integration techniques. Despite substantial progress toward realizing 3D-IC systems, a variety of design, manufacturing, packaging, and testing issues still need to be addressed before cost-effective, high-volume production can be achieved. In this article we will focus on the test challenges and solutions, highlighting a design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute (ITRI) based on the Synopsys test solution.

TSMC plans 3-D IC assembly launch early in 2013
February 02, 2012
EE Times
Leading IC foundry Taiwan Semiconductor Manufacturing Co. Ltd. plans to announce 3-D IC assembly service as a general offering at the beginning of 2013, according to Maria Marced, president of TSMC Europe.

3-D IC Standards Needed Within Six Months
February 01, 2012
EE Times Europe
Standards for 3-D chip stacks need to be in place within six months to stay ahead of chips rolling out in 2013, said a Qualcomm executive driving some of the efforts.

CEA-Leti Opens 3-D IC Packaging Service
February 01, 2012
EE Times
French research institute CEA-Leti has announced the launch of a 3-D packaging platform and service that provides industrial and academic partners with what it describes as a "mature" process for the production of 3-D interconnected products and projects.

Metallization Processes for Standardized Wide-IO Memory Applications
January 26, 2012
Advanced Packaging News
Expensive vacuum-based, dry-process tools developed for sophisticated dual-damascene applications are not the fittest solution for the manufacturing of TSVs for 3D-IC applications.

3D Integration: Not a Windfall for Test
January 19, 2012
Advanced Packaging News
After a seemingly interminable run of being “a year away,” it is clear that 3D integration (or at least the silicon-interposer-enabled 2.5D version) now offers a viable path to achieve the performance, cost, and feature integration required of next-generation mobile devices. As with any significant shift in process technology, a redistribution of the value provided by different semiconductor supply-chain elements is likely here, along with a corresponding shakeup of the winners and losers in the supply chain.

12-in Wafer Bonding Machine for 3D LSI ICs Developed
January 17, 2012
EE Times Asia
Mitsubishi Heavy Industries Ltd (MHI) has developed what it claims as the world's first fully automated 12-inch (300mm) wafer bonding machine that is capable of producing 3D integrated large-scale integration (LSI) circuits at room temperature.

Sematech to Assess 3-D Tools for Volume Production
January 16, 2012
EE Times
Sematech is preparing to assess how 3-D tools can be tuned for high-volume manufacturing needs.

The Fast Track to 3D-IC Testing
January 16, 2012
EE Times
Three-dimensional integrated circuit (3D-IC) systems offer the potential to deliver significant improvements in performance, power, functional density, and form factor over other packaging integration techniques.

IFTLE 85 2.5/3D Headlines at the 2011 RTI ASIP
January 15, 2012
Advanced Packaging News
Research Triangle Institutes 3-D Architectures for Semiconductor Integration and Packaging Conference, or 3D ASIP (as it has become known) normally finishes off the '3D conference circuit' for the year and is a good gauge of how far things have progressed in the last 12 months. At the 7th 3D ASIP in Burlingame CA a few weeks ago, there were several announcements, statements and rumors having significant impact on the 2.5/3D community.

Semiconductor Packaging Houses Gain From More Device Complexity
January 11, 2012
Advanced Packaging News
Increased I/O density on chips, power/performance requirements, yield/cost requirements and form factor constraints (mobile) are coming to push increased use of flip chip, 2.5D and 3D technologies. This trend benefits the packaging subcontractors in the semiconductor industry, argues Credit Suisse Taiwan Analyst Randy Abrams, as outsourcing rises.

3D Integration Key to 22nm Semiconductor Devices
January 02, 2012
Advanced Packaging News
3D IC integration techniques offer many benefits, the most notable being smaller footprint, lower power and higher bandwidth. From a cost standpoint, 3D’s biggest advantage is the ability to partition large, complex dies into smaller functional blocks. This improves yield and manufacturing cost equations, and enables testing/replacement of semiconductor dies prior to integration. Furthermore, individual functional blocks enable a modular design with standardized components, e.g., an ASIC manufacturer can focus on developing the ASIC and combine it with off-the-shelf memory. This allows significant reductions in complexity and cost for design and test.

TSMC Repeats Call for Foundry-centric 2.5/3D Industry
December 29, 2011
Advanced Packaging News
At the recent 7th annual RTI 3-D Architectures for Semiconductor Integration and Packaging (3D ASIP) Conference in Burlingame CA, the "buzz" centered around the presentation by TSMC's Doug Yu, senior director of integrated interconnect, who repeated the case he had made at the November Georgia Tech Interposer Conference [see "2.5D announcements at the Global Interposer Tech conference"] for the pure foundry model for 2.5 and 3DIC -- claiming that TSMC was readying to take on full beginning to end interposer manufacturing.

GSA Publishes 3D/2.5D Packaging Studies
December 27, 2011
Advanced Packaging News
The Global Semiconductor Alliance (GSA) released "3D IC Architecture: A Natural Evolution," a report sponsored by Macronix International Co. Ltd. and Etron Technology Inc. GSA also published the second edition of the 3D IC Design Tools and Services Tour Guide

Rambus, ITRI Team Up for 3D Packaging
December 20, 2011
EE Times Asia
Rambus Inc. has announced that it is partnering with the Industrial Technology Research Institute (ITRI) in Taiwan on the development of interconnect and 3D packaging technologies. The licensing company has stated that it will work with the research institute on the development of system integration using silicon interposer technology.

First 3-D IC Spec Set for Release
December 16, 2011
EE Times
JEDEC which announced a broad set of 3D IC standards development earlier in 2011 is all set to release what is touted as the first 3D IC interface standard which will be out in late December of this year (or some time in January 2012).

Rambus, ITRI to Collaborate on 3-D Packaging
December 15, 2011
EE Times
Technology licensor Rambus Inc. said Wednesday (Dec. 15) it is engaging Taiwan's Industrial Technology Research Institute (ITRI) on the development of interconnect and 3-D packaging technologies.

TSMC Goes it Alone with 3-D IC Process
December 13, 2011
EE Times
TSMC will try to go it alone with an integrated 3-D chip stacking technology as its only offering for future customers. The approach makes commercial sense for TSMC, but some fabless chip designers said it lacks technical merit and limits their options.

Test Challenges and DFM Debate Seen in 3D Chip Era
December 13, 2011
SemiMD
As the industry has lowered its chip-testing costs over the years, IC test has been somewhat predictable. But in the emerging 2.5D and 3D chip era, IC test is entering the spotlight and the traditional test flow is under the gun.

Si2 Announces Founding Members of the Open3D Technical Advisory Board
December 08, 2011
Company Press Release
The Silicon Integration Initiative (Si2) announced today the founding members of their Open3D Technical Advisory Board (TAB), which is chartered to enable interoperable 2.5D and 3D design flows with open standards, providing common formats and interfaces.

Fast Forward: Finding New Common Ground in Process Technology R&D
December 06, 2011
SEMI
The structural evolution our industry over the last decade has heightened the need for collaboration, and the semiconductor community has responded by developing new ways to work together on major transitions in device structures, patterning, materials, and manufacturing. Projecting forward five years, as we push into the sub 14nm realm, how will our collaborations change, as we tackle difficult challenges such as heterogeneous packaging, 3D device structures, nanodefectivity, and 450mm?

TSMC Gearing Up for Via-First TSV
December 05, 2011
DIGITIMES
While major IC packagers have already devoted resources on TSV (via-last) development, Taiwan Semiconductor Manufacturing Company (TSMC) is also eyeing the market with its front-end process (via-first).

IBM, Micron to Produce 3D Memory Chips
December 05, 2011
EE Times
IBM and Micron Technology announced that Micron will begin production of new hybrid memory cube (HMC) device built using the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs)—IBM's 3D chip-making process.

TSMC Gearing Up for Via-First TSV
December 05, 2011
DIGITIMES
While major IC packagers have already devoted resources on TSV (via-last) development, Taiwan Semiconductor Manufacturing Company (TSMC) is also eyeing the market with its front-end process (via-first).

Sematech Starts 3D Tech Forum
November 09, 2011
EE Times Asia
Sematech Inc. has initiated a centralized online forum, the 3D Standards Dashboard, for members of the 3D interconnect community. The forum will be a platform for the community to discuss and exchange information on standards activities.

3D-IC: Ushering in a New Era in the Semiconductor Industry
November 09, 2011
SEMI
Semiconductor packaging technology has transformed from 2D into 3D stacking. Currently, the industry is working on materials, equipment, manufacturing and product standardization to achieve technology optimization, time-to-market expedition and cost reduction. Twenty-five industry executives shared their viewpoints at the “SiP Global Summit” held by SEMI in Taiwan. The three-day event attracted around 1,060 attendees from the industry.

Invensas Acquires ALLVIA 3D-IC Packaging Technology
November 02, 2011
PCBCafe
Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc. (Nasdaq: TSRA), announced today that it has acquired the patent assets of ALLVIA, Inc. In addition, Invensas has entered into a two-year collaborative partnership with ALLVIA to further develop technology and intellectual property (IP) in the 3-dimensional integrated circuit (3D-IC) packaging space.

Chip Makers Intensify Race in 3D DRAM Market
October 15, 2011
SemiMD
The 3D DRAM race is heating up, as more companies are teaming up to share the costs and accelerate the development of the technology.

ST Rolls MEMS Using TSV
October 14, 2011
EE Times India
STMicroelectronics claims to be the world's first manufacturer to have implemented Through-Silicon Via technology (TSV) in high-volume MEMS production.

Perfecting the 3-D Chip
October 12, 2011
EE Times
You've heard the hype: The foundation of semiconductor fabrication will be transformed over the next few years as multistory structures rise up from dice that today are planar.

R&D Group Begins TSV Chip Pilot Production
October 11, 2011
EE Times
All Silicon System Integration Dresden (ASSID), a microelectronics wafer-level packaging and system integration center backed by the government of the German state Saxony and operated by the Fraunhofer IZM Institute, has begun pilot-line production of 3-D semiconductor devices with through-silicon-vias (TSVs), according to a statement issued Monday (Oct. 10) by one of its suppliers, Altatech Semiconductor SA.