Cost-efficient 3D IC wafer processing without adhesives
Monday, January 27, 2014
EE Times Asia
During a 3D TSV Summit on Minatech' campus in Grenoble, France, a resounding topic across the floor was on how to cut costs in 3D IC packaging. Disregarding IC design, there are many processes involved before dies can be stacked together. These include the manufacture of Through Silicon Vias (TSV), wafer handling and thinning, TSV reveal etching and Chemical Mechanical Planarization (CMP), then applying micro-bumps to finally stack another wafer or selected know-good dies.
UTBB FDSOI Devices Featuring 20nm Gate Length
Friday, January 10, 2014
Did you go to IEDM 2013 in Washington DC ? You may have attended to the "Advanced CMOS Technology Platform" chaired by TSMC, and listen to the FD-SOI related presentation "High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond". According with the abstract, this paper is the first time report of "high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET)." If you didn't go to Washington DC, or not familiar with FD-SOI, having a look at FD-SOI device architecture could help:
Monday, January 6, 2014
Electronic Engineering Journal
There's been lots of discussion of the silicon interposer as a way to ease us into the world of 3D-packaged ICs. The silicon interposer is the main enabler for what's typically referred to as 2.5D packaging; it acts like a high-quality micro-PCB that can be built using the silicon manufacturing infrastructure that's already in place.
China's SMIC Responds to Soaring 3D IC Market
Monday, October 21, 2013
In hopes of getting a piece of action in the rapidly growing thru-silicon-via technology-based 2.5D and 3D IC market, China's leading foundry, Semiconductor Manufacturing International Corp. (SMIC), announced Monday that it has formed an R&D and manufacturing center dedicated to vision, sensors, and 3D IC.
Xilinx, TSMC reach volume production on 28nm 3D ICs
Monday, October 21, 2013
Xilinx and TSMC have jointly announced production release of the Virtex-7 HT family, what the pair claims is the industry's first heterogeneous 3D ICs in production. With this milestone, all Xilinx 28nm 3D IC families are now in volume production. These 28nm devices were developed on TSMC's chip-on-wafer-on-substrate (CoWoS) 3D IC process that produces significant silicon scaling, power and performance benefits by integrating multiple components on a single device, the companies said.
Analog Drives Processor Architecture
Thursday, October 3, 2013
The recent port of a number of mixed signal interface IP blocks to 20nm by Synopsys Inc raises some fascinating questions on the microprocessor ecosystem. In days gone by, analog was well behind the curve. Now, USB, DDR, PCI Express, and MIPI PHY interfaces are available at what is pretty much the leading edge.
MemCon Panel: Promises and Pitfalls of 3D-IC Memory Standards
Wednesday, August 14, 2013
Much has been said about a "memory wall" that emerges when the throughput needs of the system outstrip the performance of the memory. One possible solution is to leap right over that wall with high-bandwidth 3D-IC solutions. But there's both promise and peril with emerging 3D-IC memory standards, according to panelists at the MemCon conference August 6, 2013.
Mentor and Tezzaron Optimize Calibre 3DSTACK for 2.5D/3D-ICs
Monday, May 20, 2013
WILSONVILLE, Ore., May 20, 2013--Mentor Graphics Corp. (NASDAQ: MENT) and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor® Calibre® 3DSTACK product into Tezzaron's 3D IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features. The two companies plan to extend their collaboration to include development of solutions for the silicon photonics market.
MOSIS joins push for silicon photonics tech
Monday, May 6, 2013
EE Times Asia
MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has partnered with ePIXfab, the European Silicon Photonics support centre that offers low-cost prototyping services for photonic ICs. According to the company, the venture gives MOSIS' customers access to Imec's modern fully integrated silicon photonics processes and Tyndall's advanced silicon photonics packaging technology.
Adaptive IP is the wave of the future
Thursday, May 2, 2013
In electronics, configurable and adaptive are terms often associated with field programmable gate arrays (FPGAs) and not blocks of intellectual property (IP). And just like configurable FPGAs were 20 years ago, adaptive IP is the wave of the future. More and more often, system-on-chip (SoC) designs make use of third-party IP. So much so, that surveys peg the percentage of IP content in a typical SoC at 70% or more, with many of these SoCs implemented in more advanced process nodes. At 28 nanometer (nm), process variation effects and dynamic variations due to fluctuating operating conditions may obstruct system performance or cause system instability.
Car, wireless apps push pressure sensors as top MEMS segment
Thursday, April 25, 2013
EE Times Asia
According to the recent prediction from IHS, microelectromechanical system (MEMS) pressure sensors will experience tremendous growth this year to become the leading type of MEMS device. The forecast is driven and hinges on the equally healthy market for automotive and handset markets, noted the market research company.
Semiconductor PLM - Needs to be smart for techies
Thursday, April 18, 2013
During my long career in semiconductor, EDA, I have heard, believed and experienced that this is a knowledge industry swamped with rapid innovation and technology drivers; typical manufacturing product development processes like Gantt charts and others do not apply here. The fallback is that most of the time estimations are ad hoc, based on gut-feel or expert opinion. Not only schedule, most of the processes are run by individual preferences; in other words the whole process is more people driven than process driven. Naturally, we see missed targets, re-spins, cost overruns, lost market opportunities and so on. It is said that success rate to first silicon is 0%! And we attribute the Product Lifecycle Management (PLM) issues to high complexity of designs at nanometer scale, high density, analog and digital mixed-signal and so on.
Cavendish Kinetics MEMS Gets Actual Mbps Nearer To Theoretical Mbps
Wednesday, April 17, 2013
Cavendish Kinetics has an answer to the the widening gap between actual mobile data rates and theoretically achievable data rates. GSM in the 90s achieved actual data rates close to the theoretical maximum but, ever since, the gap between actual and theoretical has widened. '4G technology supports data rates of 80Mbps,' says Cavendish Kinetics, 'but in practice delivers only 1-8Mbps for many users.'
Going 3D by Evolution Rather Than Revolution: 2.5D, 3D, 5.5D-IC and Beyond
Friday, April 12, 2013
Introduction In 2004, a visionary keynote by STMicroelectronics' Carlo Cognetti at the Napa KGD Packaging & Test Workshop entitled "Much More than Moore" proposed that "more than Moore" (i.e., the 3D-IC integration of complete, heterogeneous systems in the same package) is complementary to silicon-level integration, which is ruled by the well-known and established "more of Moore", and suggested that the final result of combining "more than Moore" and "more of Moore" is surprisingly more advanced than what is allowed by the simple progression of the technology nodes. At that time, the road to 3D-IC integration was unclear, R&D engineers at all levels of the supply chain were debating the different options, and 3D-IC was considered a technology of the future. We have made a great deal of progress, and today, 3D-IC integration has become the technology for the future rather than the technology of the future.
TSMC Responds to Samsung!
Friday, April 12, 2013
This was the 19th annual TSMC Symposium and by far the best I have attended. Finally tired of the misinformation that plagues our industry, TSMC set the record straight with wafer and silicon correlated data. TSMC shipped more than 88 MILLION logic wafers in 2012, more than any other semiconductor company, that gives them significant bragging rights which they rarely exercise. It was standing room only (I counted 1,200+ chairs) not including the 48 ecosystem partner companies manning the booths next door.
Health consciousness fuels quadruple growth for MEMS sensors
Thursday, April 11, 2013
Activity monitors such as the FitLinxx Pebble and Fitbug, for instance, are increasingly finding their way into consumers' hands as employers seek to augment their corporate wellness strategies, noted Shane Walker, senior manager for consumer & digital health research at IHS. "In the United States, this is due in part to the growth of consumer-directed healthcare plans and the Affordable Care Act, which is incentivizing insurers. These corporate programmes are opening yet another channel of distribution for new monitoring devices," he said.
3D stacking is the future of chip design, says Xilinx
Thursday, March 28, 2013
EE Times Asia
Since the beginning of semiconductor development, chip designers have stuck with Moore's Law, integrating more and more functionality onto their chips. Veteran chip architect Liam Madden, vice president of FPGA development at Xilinx, said during his keynote speech at the annual International Symposium on Physical Systems, that designers can have their 3D cake and eat it, too.
TSMC on Collaboration: JIT Ecosystem Development
Wednesday, March 27, 2013
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry's Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.
A Brief History of the Foundry Industry, part 2
Wednesday, March 13, 2013
Part 1 here. The line between fabless semiconductor companies and IDMs has blurred over the last decade. Back in the 1990s, most IDMs manufactured most of their own product, perhaps using a foundry for a small percentage of additional capacity when required. But their own manufacturing was competitive, both in terms of the capacity of fab they could afford to build, and in terms of process technology.