EDA’s Role in 2.5D/3D IC Game
E. Jan Vardaman
A debate in the industry has centered around the 2.5D or an interposer solution as an alternative to 3D ICs with through silicon vias. As the industry discusses various solutions, the picture that emerges in the near term is the use of 3D IC in combination with an interposer solution. With the relentless pressure to reduce cost with the demand of increased performance, one emerging solution is a partitioned die design that can be mounted on an interposer (choices of silicon or laminate, and possibly glass in the future) to be made. The difficulty of the IC designer is how to approach this from a system architecture perspective and compare a variety of growing packaging solutions with the technically best and most cost-effective 2.5/3D IC solution.
The use of pathfinding tools will enable designers to make better choices when faced with a myriad of options including the use of true 3D ICs, 2.5D, or some other form of stacking using package-on-package (PoP) with either a flip chip die on the bottom package, an embedded die in the bottom package substrate, or a fan-out wafer level package solution (FO-WLP).
Support from the EDA tool community will be essential and allow for the designer to think in 3D. While significant progress has been made, there are clearly improvements that are required. According to Herb Reiter of eda2asic, the lack of optimal EDA tools has caused many of the large IDM/ODMs and major fabless IC vendors to exert significant internal effort to enable engineers to design interposer solutions. This includes scripting and modification of existing EDA tools to adapt them for pathfinding, floor-planning, and design and verification of interposers.
When Xilinx started its stacked silicon interposer program in 2006, the company actually purchased design companies in order to gain the insight necessary to produce some of its first products. Not every fabless company has the financial resources to buy or fund an EDA company to enable them to do a 2.5D/3D IC design. In many ways, this is similar to the early challenges with ASIC design, when multiple IP blocks were combined with custom logic into one die. According to Cadence, 3D ICs do not need an entirely new design system, but do require new design capabilities in architectural analysis, floor-planning, place and route, thermal analysis, timing, signal integrity, IC and package co-design, especially regarding thermo-mechanical interactions, and test.
As user-friendly EDA tools help to increase the number of designers able to analyze and understand the architectural trade-off (performance, power, cost, etc.) of available alternatives and how they impact the manufacturing process (throughput, yields, quality, and reliability), they will broaden market acceptance of 2.5/3D ICs, drive yield-learning and cost-reduction efforts.
This article is based on the new 3D IC Gap Analysis: Remaining Issues, Solutions, and Market Status from TechSearch International, Inc. report describes the remaining obstacles to 3D IC, highlights the infrastructure improvements in fabricating and assembly logistics, and provides insight into the role of a research organizations are playing in closing the gap. Realistic forecasts for both interposers (2.5D) and 3D IC with TSVs are provided in units and number of wafers. Applications are provided with timelines for adoption. Detailed Powerpoints enable an accurate picture of the industry status and the accompanying full text report with references allows the reader access to a complete understanding of technology, markets, and applications.
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