RWOI 2020

2020 Winner Jaya Jagadish Corporate Vice President, Silicon Design Engineering, AMD India Engineering Lead AMD As India Engineering Lead, Jaya Jagadish is responsible for AMD’s R&D work out of India and for fostering a culture of innovation, inclusive growth and corporate responsibility at the company’s India Development Centre. Her first stint with AMD was in Austin 1994. She joined the company immediately after completing her master’s in electrical engineering from University of Texas at Dallas. She moved on from AMD to work with Mentor Graphics as a senior consultant from 1997-2000, followed by Analog Devices as a Senior Design Read More

2020 Nominee Nahomi Aoto Senior Director, Technology Development Micron Technology | Memory Japan Nahomi Aoto is a Senior Director of Micron Memory Japan. She has been serving semiconductor industry for 37 years. Aoto lead the most advanced process development for DRAM from 2000 to 2018 in Elpida as an executive officer and in Micron as a senior director after the acquisition of Elpida by Micron in 2013. Since 2018 Aoto fills the role of an ambassador of semiconductor technology to university students and professors in Japan. Aoto has organized over 50 lectures and speeches at universities for total 3000 Read More

2020 Nominee Karin Eibschitz-Segal Vice President & General Manager of Intel Israel Development Center and Intel Validation Engineering in the Design Engineering Group Intel Corporation Karin Eibschitz-Segal is vice president in the Design Engineering Group and General Manager of Intel Validation Engineering. In this role, she is responsible for delivering Intel’s promise of highest quality products. Based in Israel, Karin is leading the global Intel engineering organization responsible for functional, electrical and power/performance validation of products in post-Silicon across all market segments. In addition to her global role, Karin is the General Manager of the Intel Israel Development Center, Read More

2020 Nominee Lie-Szu Juang Head of Design and Technology Platform TSMC Lie-Szu Juang is the deputy head of Design and Technology Platform at TSMC. She leads multiple teams worldwide to enable customer design through design solutions of 3nm, 5nm, 7nm, and specialty technologies like embedded flash, HV/BCD, RF & SOI, and MRAM/RRAM. She is responsible for PDK, foundation library, design flow, and 3rd-party eco-system EDA/IP/service partners to enable 280 customers for 1000 successful project tape-outs each year. In this capacity, she contributed about $15 billion dollars, or 40% of TSMC revenue in 2019. She is well recognized in the Read More