ASIC Challenges for Wearable Sensors

Dr. Dragan Manic, Deputy Division Head, Integrated and Wireless Systems, CSEM Switzerland
Simon Gray, Head of Marketing & Sales, Integrated and Wireless Systems, CSEM Switzerland

The recent growth in the number of products using wearable sensors is nothing short of remarkable. While previous applications were limited to heart-rate measurement using a chest strap for sports, nowadays the applications are crossing over from sport into wellness and medical for telemedicine. This requires portable, real-time measurement of pulse rate, electrocardiogram (ECG) signals, respiration rate, oxygen saturation, activity levels and more.

Such applications place high demands on the electronics, with the need to integrate sensors, data acquisition chains, power management, signal processing and wireless communication into miniature packages, often with noisy signals, while maximizing battery lifetime. Such challenges are difficult to meet with standard components, and often require a systems-approach during product concept definition, and hardware-software co-design.

This article will address some of these challenges in relation to the integrated circuit (IC) design combined with a systems-approach and illustrate some possible application specific integrated circuit (ASIC) solutions via a number of practical examples such as a wireless bodyworn ECG monitor and a wrist-worn pulse monitor.

Analog front-end ASIC vs. full SoC

Wearable sensors present a unique set of challenges for the electronics design. On-board signal processing combined with small size, low power and low cost are difficult to meet  with standard components and optimal solutions require a micro-system design approach based on application specific standard product (ASSP) or fully custom ASIC. Ultra-low power ASSP/ASIC implementation is therefore an important value proposition for wearable sensors. In this article two approaches are considered for such microsystems, depending on the system partitioning and hardware-software co-design choices:

1. Multi-chip approach, combining a dedicated analog front-end (AFE) ASSP/ASIC together with an off-the-shelf microprocessor chip and off-the-shelf wireless connectivity solution. This AFE ASIC approach is illustrated below in the section on the sensor interface ASIC for heart rate and SpO2 measurement along with a wrist-worn pulse monitor application.
2. System-on-chip (SoC) integrating all functions on a single chip (sensor interface + processing + wireless connectivity). This approach is illustrated in the section on an ECG sensor interface in a SoC.

The first approach, AFE ASIC, offers the advantage of flexibility and lower non-recurring engineering (NRE) costs, by using off-the-shelf microprocessor and wireless chips while focusing the ASIC implementation on the most critical part of the system: the sensor interface.

The second, SoC approach, is the optimum approach in terms of performance, power consumption and form-factor; however less flexible since the embedded microprocessor core as well as communication standard are frozen by SoC implementation.

AFE ASIC approach

An AFE ASIC based system was developed¹ for a wrist-worn device integrated in a watch, allowing measurement of the heart rate (HR) and the pulse oxygen saturation (SpO2). The initial prototype was based on discrete electronic components, and by integrating the AFE into a single ASIC it was possible to reduce the power consumption and footprint by 50 percent while optimizing the accuracy via a dedicated analog to digital converter (ADC). The HR extraction uses the principle of photoplethysmography (PPG). An infrared (IR) light-emitting diode (LED) lights up the skin while a photodiode detects the variations of the emitted light. As this light is disturbed by blood volume changes, electrical variations in the photodiode are related to the heartbeat. The SpO2 extraction uses the absorption spectroscopy of the blood. IR and red LEDs are used alternately while a photodiode measures the incoming light. When the blood is saturated with oxygen, IR light is absorbed whereas red light is reflected and vice versa. The ratio between the amount of reflected light coming from the red LED and the IR LED into the photodiode is therefore proportional to the blood oxygen saturation.

The ASIC implements all of the functions of the analog chain including trans-impedance amplification (TIA), ambient light removal (ALR), low-pass filtering (LPF), sample-and-hold (S&H) and voltage gain amplification (VGA). LED drivers and ADC are also included as well as a sequencer for synchronization and an SPI interface (see Figure 1).

The circuit has been integrated in TSMC 0.18 μm, using a standard complementary metal–oxide–semiconductor (CMOS) process (see Figure 2). Two supply voltages are needed: 3 V for the input TIA and the LED driver and 1.8 V for the rest of the system.

The measured analogue front-end consumes only 235 μA for each of the three analog chains and an output integrated noise lower than 10 μVRMS within the 5 Hz signal bandwidth. The three ADCs consume 530 μA for an input referred noise of 18 μVRMS within a 250 Hz bandwidth and a resolution of 15 bits. The ADC results are ready after just 4 ms from switch-on allowing duty cycling of the ADCs. The LED drivers can bias the IR and red LEDs from a 200 μA proportional to absolute temperature (PTAT) current reference to respectively 20 mA and 120 mA in less than 30 μs, with noise level comparable to that of the TIA, resulting in a good balance of noise along the chain.

SoC approach

The SoC approach is illustrated with the IcyHeart circuit² (see Figure 3). This SoC contains in, a single chip, an ultra-low power signal acquisition front end with ADC for 3 lead ECG, a low power digital signal processor (DSP) and a low energy radio frequency (RF) transceiver. These features, for the first time, coexist on a single die. The SoC runs from a 1 V supply, compatible with a single alkaline cell, and is optimized for long battery life.

The state of the art 12 bits ADC based analog chain, the ECG optimized signal processing, the low power microcontroller with dedicated instructions and the ultra low power wireless transceiver turn the IcyHeart SoC into a smart and novel “sensing processing transmitting” ECG product.

The research leading to these results has received funding from the European Union’s Seventh Framework Program under grant agreement n° [286130].

Conclusion

The growth in the number of products using wearable sensors places high demands on the electronics integration. The challenges to integrate sensors, data acquisition chains, power management, signal processing and wireless communication into miniature packages, often with noisy signals, while maximizing battery lifetime are manifold. New opportunities for ASSP/ASIC/SoC implementation are open to meet such challenges. The range of solutions starting from multi-chip approach based on AFE ASIC combined with standard components to fully integrated SoC approach is possible. It is determined on the performance/power/flexibility/cost/delay system approach tradeoffs as discussed over two ASIC implantations.

Acknowledgments

The authors wish to acknowledge the contributions of CSEM’s design teams within its Systems and Integrated & Wireless System divisions for the wearable device related ASIC examples presented in this article.

Resources

¹   P. Persechini, F. Giroud, R. Gentsch, T. C. Le, C. Monneron, N. Raemy, P. F. Ruedi, P. Theurillat “Sensor Interface ASIC for Heart Rate and SPO2 Measurement”, in CSEM Scientific and Technical Report 2013, pp.116, Neuchâtel, Switzerland, 2013.

²  F. Giroud, P. Persechini, D. Séverac, B. Schaffer, C. Monneron, R. Caseiro, P.-F. Rüedi “IcyHeart, an ECG Sensor Interface in a SoC”, in CSEM Scientific and Technical Report 2012, pp.90, Neuchâtel, Switzerland, 2012.