Five years of changes in the chip industry

It’s been five years now since I joined UltraSoC as CEO, having worked in the semiconductor business for decades. We’ve come a long way since then, establishing ourselves not only in debug and optimization, where the company’s roots are, but also in emerging areas such as cybersecurity, predictive maintenance and functional safety. But what’s changed in the wider world since then?

Resurgence of ASICs and reagreggation of the value chain
The first change I’d note is the shift in the industry back to a more ASIC-style model, with systems companies designing their own silicon – or, increasingly often, collaborating closely with semiconductor players to create exactly the devices they need to power their next-generation products.

It’s interesting to think about why that is happening, and I think there are a number of reasons. First, if you have some intellectual property (whether it’s a product idea, algorithm, or other secret sauce) that you want to monetize, silicon is a very good way of doing that.

  • Underneath all the complexity, hardware design is actually a pretty well-understood discipline. We have automated design flows, highly accomplished outsourced manufacturing operations to call upon, years of data about reliability, etc
  • Silicon is quite robust against IP theft. OK, there are ways of reverse-engineering even very complicated chips… but compared to manifesting your idea via software, silicon looks like Fort Knox
  • Today’s software loads are so large and complicated, it’s often easier and quicker to innovate in hardware. This is quite a fundamental point – worth a blog in its own right – because it turns on its head everything we thought we knew about what hardware and software are “for”. This is particularly true in high-reliability and safety-critical environments, where changing a single line of code – even if it doesn’t break anything – can require revalidation/recertification of the whole kaboodle, which is irksome.

The second reason is that it’s simply easier now. The fabless model is so well established (see above) that… well, it’s just easy to get a chip made!  Good job everyone!!

The third reason is economics. In a world of “winner take all” returns there is little percentage in being “worse but cheaper”. For the internet giants building hyperscale data centers globally and spending billions on their technology; for an automotive company building the automotive platform for the next generaton of cars; for a company developing 5G handsets or basestations in a fiercely competitive market. For all of those the cost of developing a customer SoC, as daunting as it might be, is easy to justify given the scale of opportunities.

This shift has been significant for UltraSoC. One of the problems that we wrestled with back in 2015 was the fact that our products are specified by the silicon architect and delivered as semiconductor IP, and yet the greatest benefits accrue further down the development and deployment cycle. We were asking the silicon team to spend gates to help out not just the silicon validation team, but also the systems integration, software and customer engineering teams further down the line.

That challenge became even more pressing when we realized how much value we could bring to our customers’ customers, by building on-chip monitoring systems that could provide information on the behavior of THEIR products in the field. Now we were asking the architect to include a system monitoring function that wasn’t in the product spec.  We talked to the chipco’s customers: they said “Great, but you’ll need to talk to the semiconductor people”. We were going around in circles.

But as the value chain has re-aggregated, the problem has become considerably easier. Today, our customers are routinely incorporating sophisticated data gathering and analytics features in their ICs to allow fine tuning not just of the chip’s performance, but of the end-products in which they are incorporated: to make products ‘as good as they can be’ on day one of launch.

Others are going further, and using our technology for optimization throughout the product lifecycle – whether that’s to tune the performance of a data center, implementing cybersecurity on some critical infrastructure  or to perform preventive maintenance on a fleet of vehicles.

Changing platforms: Chip and system complexity
As chips have become increasingly complex we’ve witnessed a move away from a processor-centric view of the world, towards a true system-level view. For a long time now, the UltraSoC mantra has been that “it’s about the whole system, not just the core’”. The emergence of AI and machine learning is contributing to that shift; since viewing a single execution unit in isolation is meaningless in such systems. More generally, most designs we see are now “heterogeneous multicore” – with different execution units often based on different architectures – Arc, Arm, Cadence Tensilica, CEVA or RISC-V – plus hardware accelerators and custom logic.

At UltraSoC we’ve always been independent and allow the customer to choose the right combination of in-house and externally-sourced IP for their designs. Heterogeneous designs have been a good opportunity for UltraSoC’s embedded analytics technology, since it’s necessary to monitor each block in isolation and also to understand how they work together.

The emergence of RISC-V is part of that picture. I know what you’re thinking: ‘that’s an ISA, not a system-level issue’. But the point is that RISC-V gives us the opportunity to do clean sheet innovation. That’s true technically: we can build an ecosystem fit for 21st Century designs. And it’s also true commercially: because RISC-V has the potential to change the business model of the entire industry. If those aren’t ‘system-level’ issues, I don’t know what is.

No safety without security
The growing importance of cybersecurity everywhere has been hard to ignore or avoid. As our Chairman Alberto Sangiovanni-Vincentelli has stated: “In an age of autonomous vehicles, ubiquitous connectivity and increasing dependence on technology, cybersecurity is one of the top challenges for technologists.”

Part of this is about the potential consequences of a security breach. In vehicles, for example, inadequate cybersecurity can literally be life threatening: there is no safety without security. That issue is spotlighted as vehicles become increasingly autonomous. But just as important is to remember that cybersecurity is a moving target. The average lifetime of a road vehicle is eight years. Building a cybersecurity system that is going to continue to be robust for that length of time is a real challenge.

As it turns out, our core UltraSoC technology can make a substantial contribution to solving these problems. Our sentinel products sit within the underlying hardware, adding an extra layer of defense-in-depth to existing cybersecurity measures, with one big added benefit: they react at hardware speed. If we look again at the automotive example, the difference between reacting in milliseconds and responding in microseconds is substantial, and meaningful in terms of consequences.

As true today as it was five or 25 years ago: nothing stands still, especially in the wonderful world of technology.


About Rupert Baines
CEO, UltraSoc |

Rupert is a 30-year veteran of the global semiconductor and communications industries, and has previously held senior roles in both start-ups and prominent trans-national companies. Before joining UltraSoC he was VP of Strategic Marketing at Mindspeed following that company’s acquisition of Picochip (now part of Intel), where he had served as VP of Marketing. His CV also includes spells at first:telecom, Arthur D Little and Analog Devices, where he played a key role in the development and mass-market adoption of digital subscriber line (DSL), the most common broadband access technology in use around the world today. Rupert is a Fellow of the IET.