2025 WLI WISH Conference

Liya Liu [AI Track]

Senior Member of Technical Staff

AMD

Dr. Liya Liu is a Senior Member of Technical Staff at Advanced Micro Devices (AMD), where she has been contributing for over 12 years. Her current work primarily focuses on formal verification in the Security IP team, along with design verification (DV) methodology exploration. Prior to her industry career, she was a Research Assistant in the Hardware Verification Group (HVG) at Concordia University, specializing in theorem proving, and earned her Ph.D. in 2013.

She also holds an M.A.Sc in Signal Processing from Wuhan Technical University of Surveying and Mapping (1999) and an M.Eng from Concordia University (2009).

Rachana Maitra [AI Track]

Senior Principal Engineer

Marvell Technology

Rachana Maitra is a Senior Principal Engineer, Corporate SDL lead at Marvell Technology Inc. She has been in the tech industry for over 26 years, starting at Intel in 1999 as a verification/validation engineer. In 2006, she joined Marvell and went on to leading pre- and post-silicon validation efforts covering 20+ products, across multiple business units. In 2022, Rachana transitioned to the Corporate SDL team and took on the responsibility of leading Marvell’s proactive process and strategy/toolset development for product security assurance across the company.

Rachana earned MSE in Electrical Engineering from Arizona State University. She regularly volunteers at a hospice care facility and at a local Bengali school. In her spare time, Rachana enjoys spending time with family!

Rachel Son [AI Track]

Senior Engineer

SanDisk

Rachel Son is a Senior Engineer in Technology Development at SanDisk, where she drives AI-based trim optimization and advances innovation in high-endurance, read-intensive flash memory for AI-inference applications.

She brings a unique technical background, holding a B.S. in Civil Engineering from Iowa State University and an M.S. in Electrical and Computer Engineering from North Carolina State University. Outside of work, she enjoys road cycling and running.

Carmen Galotta [Design Track]

Physical Design Engineer

STMicroelectronics

Since joining ST in 2021, Carmen has been driving innovation in design implementation, overseeing the RTL-to-GDS flow with a focus on signoff timing, equivalence checking, power analysis, and optimization. Her deep expertise in digital physical design and low-power methodologies enables ST to deliver cutting-edge, high-performance solutions that meet customer needs. As Direct Responsible Individual (DRI), she ensures seamless collaboration across multi-site engineering teams and maintains strong client relationships.

Carmen holds a double master’s degree from the Micro and Nano Technologies for Integrated Systems (MNIS) program, awarded jointly by Politecnico di Torino, Phelma Grenoble, and École Polytechnique Fédérale de Lausanne (EPFL), reflecting a solid foundation in advanced integrated system technologies

Sangeeta Raste [Design Track]

Senior Manager, PMTS Silicon Design

AMD

With over 25 years in the semiconductor industry, Sangeeta Raste is a seasoned expert in ASIC and FPGA digital logic design. As a senior manager at AMD, she leads a high-speed memory I/O design team. Her experience spans at Altera, Intel, AMD as a high speed IP designer and leader, where she worked on many high speed designs and cutting edge technologies. She has a good track record of managing teams globally and delivering many tapeouts and projects successfully.

In addition to her technical job, she is actively involved in women’s community events to promote girls in technology and engineering, Sangeeta mentor girls in technology and engineering by leading engineering workshops through SWE and other organizations.

Siying Liu [Design Track]

Senior MTS Silicon Design Engineer

AMD

Siying Liu is a Senior MTS Silicon Design Engineer at AMD, specializing in IP verification, methodology, AI and tooling. With over 13 years of experience in design verification, she is an expert in IP and system-level verification of complex cross-die and cross-socket network-on-chip (NoC) in the control plane, as well as the development of related tools, such as NoC deadlock analysis and NoC topology design automation. Siying has pioneered the use of formal verification methods and machine learning to enhance verification quality and design efficiency. She also engaged in verification and compiler improvement of power state controller block.

Siying holds a Master’s degree in EE from Xidian University in China.

Ellie Chen [Process Track]

Hardware Product Engineer

Meta

Ellie Chen is a hardware product engineer at Meta, specializing in the development and deployment of liquid cooling solutions for hyperscale infrastructure. She leads product lifecycles across multiple system scales — from standalone rack systems with in-row CDUs to cluster-level architectures with facility-integrated cooling — focusing on manufacturability, validation, and operational scalability. Ellie collaborates closely with design and operations teams to deliver high-quality, cost-optimized hardware for compute, storage, and AI/ML workloads. She has led performance validation and helped establish engineering standards supporting the global deployment of over 100,000 systems. She also contributes to the Open Compute Project, aligning Meta’s cooling strategy with broader industry trends. With over a decade of experience, Ellie previously led mechanical and system design at Supermicro.

She holds a master’s degree in mechanical engineering from National Taiwan University and enjoys mentoring engineers, exploring new technologies, and hiking Texas trails.

Jasmine Chang [Process Track]

Process Engineer

Micron Technology

Jasmine Chang is a Dry Etch Process Engineer at Micron Technology, where she has been contributing to advanced DRAM process development since 2014. She has worked on multiple technology nodes, including 1α, 1β, and 1γ, with a focus on EUV patterning and integration across critical DRAM etch modules. Jasmine’s work bridges innovation and manufacturability, developing scalable etch solutions while enhancing throughput and enabling efficient high-volume production. She plays a key role in implementing intelligent process control strategies that accelerate development cycles and support early-stage manufacturing readiness.

Jasmine received M.S. degree in applied chemistry from National Chi Nan University in 2014.

Qi Wang [Process Track]

Distinguished Engineer

Marvell Technology

Qi Wang is a Distinguished Engineer at Marvell Technology Inc., working in the Central CAD & Design Service group. With over 24 years of experience in physical verification, she has specialized in developing advanced CAD methodologies for physical design verification. The flow developed by Qi’s team has enabled design teams to successfully tape out over 80 chips across more than 10 technology nodes, collaborating with major foundries including TSMC, Samsung and GLOBALFOUNDRIES. Her expertise spans physical verification, layout automation, and tapeout signoff, all focused on enabling seamless integration and optimization of complex semiconductor technologies.

Qi holds a Master of Engineering in Electrical Engineering from Santa Clara University.

Anju John [System Track]

Senior Hardware Systems Engineer

Meta

Anju is a Senior Hardware Systems Engineer at Meta, specializing in data analytics and automation solutions for monitoring AI/HPC systems, thus enabling large-scale hardware health analysis. She designs and implements data pipelines, analytics dashboards, and reliability models to extract insights on network, compute, and interconnect technologies. She focuses on performance monitoring of network hardware and optical technologies, supporting the sustaining workflows and troubleshooting of network hardware fleet.
Anju has over a decade of industry expertise across domains such as Network operations, network security, automation and analytics infrastructure development. Prior to Meta, she has worked at Ericsson and Trend Micro developing validation strategies and supporting sustaining operations for networking and security platforms.

She holds a master’s degree in electrical engineering specializing in Networking and Embedded Systems.

Lucy Yu [System Track]

Principal Hardware System Development Program Manager

Microsoft

Lucy Yu is a Principal Hardware System Development Program Manager at Microsoft Cloud + AI, where she leads the development and deployment of cutting-edge Cloud AI systems and Azure networking solutions. Since joining Microsoft in 2020, she has driven innovation through silicon integration, system development, and end-to-end solution delivery. Prior to Microsoft, Lucy spent 15 years at Intel advancing compute, storage, and FPGA system technologies for hyperscale platform solutions.

Lucy holds an M.S. in Computer Engineering from the University of Waterloo, B.S. and M.S. degrees in Electrical Engineering from Huazhong University of Science and Technology.

Xiling Sun [System Track]

Principal Firmware Engineer

Microsoft

Xiling Sun is a principal firmware engineer at Microsoft, where she focuses on firmware security in the Azure Hardware Systems and Infrastructure group. She led the architecture and development of Hydra, a novel secure BMC solution announced at the OCP’22 Global Summit. With over 13 years of industry experience, Xiling brings deep technical expertise and leadership across storage controllers, accelerators, and cloud hardware security. Her previous roles include developing storage controller firmware at PMC-Sierra and Microchip, and serving as a tech lead at SK Hynix America’s Memory Solution Research Lab, where she enabled pioneer accelerator architecture for computational storage.

Xiling holds a master’s degree in computer engineering from New York University.

Isabelita Camaclang [Test Track]

Member of Technical Staff

AMD

Isabel is a Member of Technical Staff at AMD. As a member of the CORES team, she’s been contributing to designing the fastest and best performing CPUs and GPUs for gaming, research, and automotive use. Before joining AMD, she started her career at Sandisk where she architected Memory BIST and Scan test of memory controllers.

Isabel earned her Bachelor of Science in Computer Science from California State University East Bay and her Master of Science in Computer Engineering from Santa Clara University. Lastly, she is an origami, taiko, and 3D printing enthusiast.

Manvitha Pannala [Test Track]

Technical Program Manager

AMD

Manvitha is a Senior Silicon Design Engineer at AMD, currently serving as the Technical Program Manager for Central Engineering, focusing on High-Speed IPs for the MI450 Data Center GPU. In this role, she leads cross-functional efforts to drive silicon design execution and program alignment across critical IP blocks. Prior to this, Manvitha was the technical lead for third-party security IPs, including AEMC, and was responsible for the development and power integrity verification of third-party IPs such as multiple generations of USB and PCIe.

With approximately four years of experience in the semiconductor industry, she began her career at Intel, before joining AMD in 2022. Manvitha holds a Master’s degree (Thesis) in Electrical Engineering from Arizona State University. Outside of work, she enjoys traveling, cooking, sketching, and spending quality time with her family.

Mayura Padmanabhan [Test Track]

Technical Project Manager

SEMI

Mayura Padmanabhan has been a Technical Project Manager with SEMI since 2023. She leads the Semiconductor Manufacturing Cybersecurity Consortium (SMCC) technology community. Prior to SEMI, she worked as a Probe Engineer in Smart Manufacturing and AI at Micron Fab10 in Singapore, where she worked on yield improvement and test time reduction projects.

Mayura holds a Master of Science in Electrical Engineering (MSEE) from the National University of Singapore and a Bachelor of Engineering in Electronics and Communications from Anna University, India where she was a University Rank holder and received the Best Outgoing Student Award and a U. She is a PMI Certified Project Management Professional, Agile Practitioner, and Scrum Alliance Certified Advanced Scrum Master. She is also a proud founding member of the Women@SEMI Employee Resource Group at SEMI. She is an active Toastmaster passionate about mentoring young girls in STEM and enjoys painting folk art.

Pragya Nahar [Test Track]

Director, Test Engineering

Infineon Technologies

Pragya Nahar is the Director of Test Engineering for IoT Wireless and Compute at Infineon Technologies. She currently leads the test engineering efforts for wireless connectivity products. She joined Cypress Semiconductor in 2004 (acquired by Infineon in 2020). Pragya has 20 years of experience in leading the development of ATE test solutions through generations of silicon.

She received her Bachelor’s degree in Electronics and Communication Engineering and Master’s in Microelectronics and VLSI design from India. Her passion lies in leveraging her expertise to drive innovation and excellence in the field of test engineering.

Sujata Paul [Test Track]

Principal Silicon Reliability Engineer

Microsoft

Sujata holds a Ph.D. in Physics from North Carolina State University and brings over a decade of experience from industry leaders like IBM, Cisco, and Marvell. She has worked on everything from device and component reliability to cutting-edge optics for data centers—and now focuses on AI accelerator and compute chip reliability at Microsoft.

Passionate about continuous learning, Sujata is deeply interested in design, technology, process, quality, and semiconductor reliability. She lives in Fremont, CA, with her husband and teenage son, and enjoys cooking, traveling, and reading in her free time.

Xia Ju [Test Track]

Senior Manager, Product Development Memory Technology

SanDisk

Xia has over 12 years of experience in the semiconductor industry, holding a master’s degree in Electronic Science and Engineering from Southeast University. She has focused on reliability research and reliability test automation, playing a key role in various projects that enhance the quality and performance of semiconductor products. Passionate about the application of new technologies, Xia is dedicated to developing innovative solutions to meet evolving market demands.