November 10, 2026
WISH, GSA WLI’s premier technical conference, is an inspiring celebration of innovation and empowerment. The event welcomes around 1,000 attendees, including industry luminaries, visionary entrepreneurs, and brilliant university students in STEM, and showcases the evolving landscape of technology. Attendees experience powerful keynotes from trailblazers who are reshaping the tech world and celebrate award ceremonies honoring extraordinary women who break the glass ceiling and those paving the way for future generations. It is a unique opportunity to connect with like-minded professionals and build valuable relationships to help propel careers forward. WISH champions gender parity and celebrates the remarkable achievements of women in technology—bringing together a movement that is transforming the industry!
EMCEE
Annelise McCarthy is an international speaker, LinkedIn Top Voice, and communication expert specialising in confidence-led communication and leadership presence. Over the past decade, she has coached professionals, founders, executives, and elite performers to communicate with clarity, credibility, and authority. From CEOs to Olympians, Annelise equips high achievers with practical tools to articulate their value, command rooms, and lead with conviction.
With more than 15 years of experience and a background in education, law, and competitive public speaking, she has worked with thousands of professionals across 20+ industries and 15 countries. Today, she leads a global community of 300,000+ who follow her modern, no-BS approach to communication and impact. Her core belief is simple: How you communicate determines your influence. She challenges every audience to use their voice with clarity and conviction, because the world does not change when capable people stay quiet.
Program
Registration and Networking Breakfast
Welcome Remarks – Annelise McCarthy
Opening Invited Keynote/Fireside Chat
Dr. Lisa Su Woman of Innovation Award
Panel: “Women Leading the Semiconductor Revolution: Redefining Leadership for What the Next Decade Demands”
Join us for a forward-looking panel discussion spotlighting the women shaping the next era of semiconductor leadership. As the industry navigates unprecedented complexity and rapid transformation, these influential leaders will share how they are guiding their organizations through change while positioning themselves for the future. In this session, they will share their personal journeys, keys to success, and insights on how to become effective leaders in the tech world. The discussion will explore the critical leadership skills needed in a world defined by AI acceleration and an intensifying global landscape. Don’t miss this opportunity to gain strategic insight into what the next decade demands from today’s semiconductor leaders.
- Jennifer Lloyd / President & CEO / Power Integrations
- Jutta Meier / CEO & CFO / IQE
- Rani Borkar / President, Azure Hardware Systems and Infrastructure / Microsoft
Smoothie Break and Transition to Breakout Sessions
Sponsored by
Artificial Intelligence (AI) in Hardware
"Accelerating FPGA Physical Design Closure through Generative AI"
- Mrunal Sagare / Physical Design Engineer / Lattice Semiconductor
"Agents on Rails: Deterministic AI for Chip Sign-Off"
- Abhishikta Pandit / Principal Silicon EDA Infrastructure Engineer / Meta
"ARTEMIS: A Multi-Agent AI System for Automated Root-Cause Analysis and Optimization of RTL Verification Workflows"
- Nupur Bhonge / Solutions Architect / Amazon Web Services (AWS)
"Formal Verification in the Age of Generative and Agentic AI"
- Pallavi Atha / Principal Formal Verification Engineering Manager / Astera Labs
"From Specification to Proof: AI Agent Automation of AEP and FPV Workflows"
- Liya Liu / Senior Member of Technical Staff / AMD
"Keep Your Data, Share the Model: Federated Learning for Privacy-Preserving Hardware Anomaly Detection Across Distributed Fleets"
- Cynara Justine / Senior Software Engineer / Microsoft
Design Technology
"Achieving Glitch Power Visibility via Delay-Shifted Analysis for Actionable Power Optimization"
- Neetu Mehta / Senior Silicon Design Engineer, India / AMD
"Constraint-Driven Routing Closure for High-Frequency Mixed-Signal Designs"
- Rajashri Lakhotia / Senior Staff Manager / Lattice Semiconductor
"Executable Interrupt Specifications: Managing Control-Plane Complexity in Disaggregated Server SoCs"
- Sindhu Amireddy / Principal SoC Architect / Microsoft
Process Technology/Packaging/Assembly Technology
"Failure Analysis Challenges of Advanced Packaging"
- Susan Li / Technical Director of Failure Analysis / Marvell Technology
"Mechanism-Driven Etch-Passivation Balance Engineering for LCDU Convergence Across Hybrid EUV Geometries"
- Jasmine Chang / Dry Etch Process Engineer / Micron Technology
"Split-Gate Inter-Poly Architecture for Electrical Gate Leakage and Mechanical Wafer Warpage Optimization in Trench FP-MOSFETs"
- Irene Monica Lasar / Senior Technology Development Engineer / STMicroelectronics
System Technology
"Making True Single-Stage EV Charging Practical: System-Level Redesign of a Dual-Active-Bridge On-Board Charger Enabled by Bidirectional GaN and Closed-Form Control"
- Sara Bourouga / Technical Marketing & Application Support Engineer, EMEA Automotive organization / STMicroelectronics
"Trivializing Chip Reset Timing: A Novel Technique for SoC Backend Closure"
- Aradhana Kumari / Staff Engineer in Research & Innovation Team, Crolles, France / STMicroelectronics
"Under the Hood of Hardware Systems for Accelerator-Aware Workloads: From Lab to Fleet"
- Vidya Samyuktha / Principal Hardware Systems Engineer / Microsoft
Test/Validation
"Capping with Confidence: A Test & Validation Framework for Power Savings and a Lower Data-Center Carbon Footprint"
- Smitha Kashyap C / Principal Systems Engineer / Microsoft
"On-Device Cryptographic Key Provisioning for PSA Level 3 MCU: Secure Firmware Synthesis and Attestation"
- Lalitha Abraham / Principal Test Development Engineer / Synaptics
"Scaling Electro-Optical Test and Reliability Validation of Silicon Photonics for AI and Hyperscale Data Centers"
- Tala Sidawi / Senior Product Reliability Engineer / Ayar Labs
Main Stage Panel: "From First Role to Leadership: Real Stories of Award-Winning Women in Tech"
Featuring recipients of the Lisa Su Award, Women of Influence Award, Rising Women in Semi Award, and Female Up & Comer Award, this panel brings together women at every stage of leadership to share candid stories, career insights, and lessons learned along the way.
Every career journey is unique, yet the challenges of building confidence, navigating change, seizing opportunities, and growing as a leader are shared across generations. In this candid conversation, past Women’s Leadership Initiative (WLI) Award recipients representing every stage of the career spectrum, will reflect on the defining moments that shaped their professional journeys.
Panelists will share insights on overcoming obstacles, building visibility, embracing career pivots, developing leadership skills, and supporting the next generation of women in technology. Through personal stories and practical advice, attendees will gain valuable perspectives on navigating their own careers while helping create a more inclusive and empowering future for women in semiconductors.
- An Mei Chen / VP of Engineering and Site Lead for Vietnam R&D Center / Qualcomm
- Julie Sheridan Eng / EVP, Optical Components and Chief Technology Officer / Coherent
- Manisha Gambhir / Senior Director of Engineering, Analog Mixed Signal / Marvell Semiconductor
- Yanfang Le / Principal Network Architect / AMD
Lunch & Networking
Welcome Back
Panel: "AI as a Catalyst: Building Resilient Teams and Inspiring Leadership"
As AI capabilities become increasingly integrated into engineering workflows, leaders have an opportunity to rethink how work gets done, how teams collaborate, and how careers continue to grow. The challenge is not simply adopting new tools, but ensuring they enhance human creativity, judgment, and problem-solving while supporting sustainable ways of working.
This panel will explore how AI is influencing engineering practices, leadership approaches, and workforce development across the semiconductor industry. Our esteemed panelists will share inspiring perspectives on evolving skill sets, effective learning strategies, and the leadership practices that help teams adapt with confidence. The discussion will examine how organizations can use AI to reduce routine work, strengthen innovation, and create more opportunities for engineers to focus on high-value contributions.
Drawing on real-world experience, panelists will discuss how to foster resilient, high-performing teams, support continuous career growth, and build inclusive environments where engineers can thrive alongside rapidly advancing technologies. Attendees will leave with practical insights and a renewed sense of purpose for leading through change while sustaining engagement, well-being, and long-term impact.
- Alexis Björlin / Chief Strategy Officer / General Catalyst
- Qi Wang / Distinguished Engineer / Marvell Technology
- Viviana D'Alto / Artificial Intelligence SW & Tools Research Director (SRA/SCIS) / STMicroelectronics
Awards Presentation
- Rising Women in Semi Award Presentation (sponsored by Sandisk)

- Female Up & Comer Award Presentation (sponsored by AMD)

- Designing the Difference Award Presentation (sponsored by Microsoft)

WISHing Wall Presentation and Closing Remarks
Sponsored by
Networking and VIP Reception
Sponsored by
Speakers

Alexis Björlin
General Catalyst
Alexis Björlin
Chief Strategy Officer
General Catalyst
Alexis Björlin is General Catalyst’s Chief Strategy Officer. In this role, Alexis works across our transformation businesses to build a flywheel for scaling, establishing, and executing our strategy to build the highest-performance, lowest-cost intelligence infrastructure for our overall AI transformation agenda.
Alexis brings a career that has run straight through the infrastructure of AI. At Nvidia, she was SVP & GM DGX Cloud, responsible for building Nvidia’s cloud business and scaling their internal multi-cloud infrastructure to one of the largest AI fleets in the world. Prior to Nvidia, Alexis led Infrastructure at Meta, where her team was responsible for hardware-software co-designed systems, including AI systems, compute and storage platforms, kernel, and custom silicon. She was an SVP and GM at Broadcom, and led three Data Center business units at Intel spanning Ethernet, High Performance Computing, and Silicon Photonics, and spent eight years as President of Source Photonics, building an optoelectronics manufacturing business across China and Taiwan.
Alexis currently serves on the board of Micron Technology and has previously served on the Boards of Digital Realty [NYSE:DLR], Astera Labs, Celestial.AI, and the Global Semiconductor Association (GSA). She holds a B.S. in Materials Science from MIT and a Ph.D. from UCSB.
Alexis Björlin
Chief Strategy Officer
General Catalyst

Audrey Charles
Lam Research
Audrey Charles
SVP Corporate Strategy, Advanced Packaging, Lam Research and President, Lam Capital
Lam Research
Audrey Charles is senior vice president of corporate strategy, advanced packaging, and president of Lam Capital at Lam Research. In this role she leads the development of our long term strategy in support of the company’s sustainable outperformance. She is also responsible for accelerating the company’s market-leading position in advanced packaging by delivering differentiated technology and support to customers across Lam’s product portfolio.
Additionally, Audrey oversees Lam’s Corporate Development team and investment arm, Lam Capital, which invests in disruptive companies that advance the semiconductor ecosystem through next generation industrial automation, technology and product innovation, and new market opportunities. She brings a broad base of experience to her role, including engineering, customer technology management and enterprise leadership roles in investor relations and Human resources. Since joining Lam in 1995, she has served in a range of leadership positions including senior vice president of Corporate Development and Strategic Planning.
Audrey earned an M.B.A. from the MIT Sloan School of Management and a B.S. in applied physics from Dublin City University.
Audrey Charles
SVP Corporate Strategy, Advanced Packaging, Lam Research and President, Lam Capital
Lam Research

An Mei Chen
Qualcomm
An Mei Chen
VP of Engineering and Site Lead for Vietnam R&D Center
Qualcomm
Dr. An Mei Chen is Vice President of Engineering and site lead for Qualcomm’s Vietnam R&D Center, where she leads AI research, SoC design, software engineering, and systems. She is building a multidisciplinary organization that connects fundamental research, platform prototyping, semiconductor design, and software development, while developing regional talent and strengthening collaboration across industry and academia.
During more than two decades at Qualcomm, Dr. Chen has led innovation across wireless communications, multimedia, AI, IoT, and automotive technologies. She has built and led global, cross-functional teams, helping move ideas from early research through prototyping and toward real-world deployment. Her career reflects a consistent commitment to combining technical innovation with practical impact.
Dr. Chen has also played an important role in growing innovation ecosystems across Asia. She launched Qualcomm’s startup incubation programs in Asia and led university research collaborations across the region. Through these efforts, she has supported entrepreneurs, researchers, and students in translating promising ideas into meaningful technologies and opportunities.
A prolific inventor, Dr. Chen holds over 500 international patents and has authored numerous technical publications and book chapters. She received the 2024 GSA Women of Influence Award and the UC San Diego Jacobs School of Engineering Distinguished Alumni Award. She earned her B.S. with honors and Ph.D. in Electrical and Computer Engineering from UC San Diego.
Beyond her technical leadership, Dr. Chen is committed to developing people and expanding opportunities for women, first-generation students, and underrepresented innovators. Through mentoring and advisory service, she supports innovation, entrepreneurship, and STEM education. At WISH, she hopes to bring a global perspective shaped by building technologies, teams, and organizations across disciplines and regions. Her journey offers practical lessons on embracing change, pursuing meaningful opportunities, and helping others grow into leadership.
An Mei Chen
VP of Engineering and Site Lead for Vietnam R&D Center
Qualcomm

Jennifer Lloyd
Power Integrations
Jennifer Lloyd
President & CEO
Power Integrations
Dr. Lloyd joined Power Integrations as President, CEO and a member of the Board of Directors in July 2025. Prior to that, she served in a succession of engineering and business roles spanning nearly three decades at Analog Devices, Inc., a global semiconductor leader. Most recently, she was Corporate Vice President leading the company’s MultiMarket Power business unit; prior roles included leadership of Analog’s Precision Franchise and its Healthcare and Consumer Business. Jen’s technical background is in developing data converter (ADC, DAC) and serial interface integrated circuit products and technology for which she holds 9 US patents and several publications, including a Best Paper Award at the International Solid-State Circuits Conference (ISSCC). She has served on the technical program committee for the IEEE Custom Integrated Circuits Conference, the IEEE Symposium on VLSI Circuits, and the ISSCC Imager, Medical, MEMs and Display (IMMD) Program Committee. Jen also served on the Board of Power Integrations from 2021 to 2022, and the Advisory Board for the Dean of Engineering at WPI (Worcester Polytechnic
Institute). Dr. Lloyd holds S.B., S.M. and Ph.D. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology (MIT).
Jennifer Lloyd
President & CEO
Power Integrations

Julie Sheridan Eng
Coherent
Julie Sheridan Eng
EVP, Optical Components and Chief Technology Officer
Coherent
Julie Sheridan Eng is the EVP, Optical Components and Chief Technology Officer at Coherent. She was named Chief Technology Officer (CTO) of Coherent in 2022. Prior to becoming CTO, Dr. Eng served as Senior Vice President and General Manager of the Optoelectronic Devices and Modules Business Unit, leading engineering, product management, and operations for VCSELs, InP lasers and detectors, and CMOS/BiCMOS ICs for datacom and 3D sensing.
Prior to Coherent, she held senior leadership roles at Finisar, including EVP and GM of 3D Sensing and EVP of Datacom Engineering, where her teams launched hundreds of fiber optic transceiver products and delivered multiple industry firsts. She began her career at AT&T Bell Laboratories/Lucent/Agere, leading development of laser-based datacom transceivers.
Dr. Eng is a Past Chair of the IEEE Women in Engineering Committee and serves on the Board of Directors of Optica. She has published extensively, holds six U.S. patents, and is a frequent invited speaker. She was named an Optica Fellow in 2022, elected to the National Academy of Engineering in 2025, and received the 2025 Dr. Lisa Su Woman of Innovation Award from the Global Semiconductor Alliance.
She holds a B.A. in Physics from Bryn Mawr College, a B.S. in Electrical Engineering from Caltech, and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University.
Julie Sheridan Eng
EVP, Optical Components and Chief Technology Officer
Coherent

Jutta Meier
IQE
Jutta Meier
CEO & CFO
IQE
Jutta is an experienced industry executive who has held senior positions at global semiconductor companies for close to 30 years.
She joined IQE in January 2024 from Intel Corporation and she has held senior executive roles at GlobalFoundries and AMD. Her expertise spans corporate strategy, capital allocation, governance, M&A, transformation and global manufacturing operations.
In addition to leading IQE, she serves on the UK Government’s Semiconductor Advisory Panel and the UK Semiconductor Centre’s Interim Steering Group, helping shape the future of the semiconductor industry. She holds an Master’s degree in Business Administration from the Dresden University of Technology.
Jutta Meier
CEO & CFO
IQE

Manisha Gambhir
Marvell Semiconductor
Manisha Gambhir
Senior Director of Engineering, Analog Mixed Signal
Marvell Semiconductor
Dr. Manisha Gambhir is a Senior Director and Technology Architect at Marvell Semiconductor, where she leads global teams developing high-performance, mass-production-ready mixed-signal IPs in advanced process technologies. Her work has been instrumental in enabling breakthrough products across AI infrastructure, networking, storage, and automotive markets. In recognition of her technical leadership and industry impact, she was the recipient of the 2025 GSA Rising Woman in Semiconductor Award.
Dr. Gambhir began her career at Texas Instruments as an analog design engineer and earned both her M.S. and Ph.D. in Electrical Engineering from Texas A&M University. An accomplished inventor, she holds multiple U.S. patents spanning circuit design and system architecture. Since joining Marvell, she has advanced through successive technical and leadership roles, building a portfolio of transformative technologies and products while
establishing herself as a respected thought leader within the company and the broader semiconductor ecosystem. At Marvell, she serves on several strategic committees, including the Patent Committee, Marvell Innovation Contest, Marvell Engineering Technical Conference, and University Engagement Committee, helping drive innovation, technical excellence, and talent development. She is also a frequent speaker and panelist at industry conferences and technical forums.
Beyond her business and technology leadership, Dr. Gambhir is deeply committed to mentoring the next generation of engineers and leaders. She is actively involved in early career and university programs, and industry-wide women leadership initiatives such as the GSA Women in Hardware Mentorship Program. Through GSA, Manisha has gained valuable opportunities for mentorship, executive education, and meaningful connections with trailblazing women in the semiconductor industry. She actively pays this forward by championing STEM education, both within Marvell and across the broader ecosystem, fostering a more diverse and inclusive technical community.
Manisha Gambhir
Senior Director of Engineering, Analog Mixed Signal
Marvell Semiconductor

Qi Wang
Marvell Technology
Qi Wang
Distinguished Engineer
Marvell Technology
Qi Wang is a Distinguished Engineer at Marvell Technology, where she leads the Central Physical Verification CAD team. With over 25 years of experience at the intersection of semiconductor design and engineering leadership, she has built a career defined by technical innovation, team empowerment, and the deliberate integration of AI into complex engineering workflows.
Qi’s team has enabled physical verification flows for more than 80 chip tapeouts across 10+ technology nodes—including TSMC A16, N2P, N3P, SoIC, and CoWoS—collaborating with major foundries such as TSMC, Samsung, and GLOBALFOUNDRIES. She pioneered Marvell’s 3DIC physical verification methodology, enabling the company’s first SoIC tapeout, and co-developed a novel multi-level ESD verification framework for heterogeneous stacked chiplet systems, for which she has filed a provisional patent.
A firm believer in AI as a force multiplier, Qi has led the development of Marvell’s AI-enabled PV Assistant platform—a suite of tools that eliminates manual verification work through natural language interfaces, ML-based runtime prediction, and autonomous agentic pipelines. She has driven a goal of 20% efficiency and quality improvement across PV flows through AI adoption, and has influenced EDA vendor roadmaps at Siemens and Synopsys through strategic technology roadmap meetings.
As a leader, Qi invests deeply in growing her team. She delegates meaningful ownership to engineers at all levels, mentors junior engineers on AI integration and innovation, and fosters a culture where ideas move from concept to production. She completed Marvell’s Technical Leadership Mentoring Program (TLMP) and has participated in the Marvell Elevate Mentoring for Women Leaders program.
Qi has presented at WISH GSA, SNUG, DAC, Siemens U2U, and Marvell Connect. She holds a Master of Engineering in Electrical Engineering from Santa Clara University.
Qi Wang
Distinguished Engineer
Marvell Technology

Rani Borkar
Microsoft
Rani Borkar
President, Azure Hardware Systems and Infrastructure
Microsoft
Rani Borkar is President of Azure Hardware Systems and Infrastructure at Microsoft, where she leads the teams responsible for planning, architecting, developing, and deploying the end-to-end hardware and infrastructure that powers Microsoft Azure, from silicon and systems to supply chain and global capacity deployment.
A pioneer in the semiconductor industry, Borkar brings more than 35 years of experience shaping some of the most significant platform shifts in modern computing, including the rise of the PC, mobile computing, multicore processors, and today’s era of cloud and AI.
At Microsoft, Borkar has been instrumental in strengthening Azure’s position as a leading enterprise cloud platform serving more than 95% of the Fortune 500. As part of that work, she built Microsoft’s first-party silicon portfolio, including Cobalt, Azure’s Arm-based CPU, and the Maia AI accelerator.
Prior to joining Microsoft, Borkar spent 27 years at Intel, where she served as Corporate Vice President and General Manager in the Product Development Group, leading silicon product strategy for industry-defining processor families including Intel Xeon, Core, Atom, Pentium, and Celeron. She also held senior leadership roles at IBM, including Vice President of OpenPOWER Development.
She serves on the boards of Applied Materials and the Global Semiconductor Alliance (GSA).
Borkar holds bachelor’s and master’s degrees in physics from the University of Mumbai, a master’s degree in electrical engineering from the Oregon Graduate Institute.
Rani Borkar
President, Azure Hardware Systems and Infrastructure
Microsoft

Viviana D'Alto
STMicroelectronics
Viviana D'Alto
Artificial Intelligence SW & Tools Research Director (SRA/SCIS)
STMicroelectronics
Viviana D’Alto is Director of Artificial Intelligence Software & Tools Research at STMicroelectronics and a technology leader with more than 36 years of experience driving technological advances across the semiconductor industry. She graduated summa cum laude in Physics from the Università degli Studi di Milano, with a specialization in Electronics, and has built a multidisciplinary career spanning system architecture, algorithms, computer vision, multimedia systems, artificial intelligence, and technology strategy.
Throughout her career, Viviana has combined innovation, technical expertise, and collaborative leadership, contributing both personally and through the teams she has led to technologies embedded in semiconductor products deployed in millions of devices worldwide across imaging, multimedia, navigation, and mobile platforms. Over the last decade, she has been at the forefront of ST’s Edge AI transformation, championing the vision of bringing neural-network intelligence directly onto resource-constrained embedded devices.
She initiated and led the research program that evolved into ST Edge AI Core Technology, a company-wide foundation that enables the deployment of AI across microcontrollers, microprocessors, and smart sensors. Today, this technology supports more than 160,000 active customer projects worldwide and serves as a cornerstone of ST’s embedded AI strategy. Since 2022, Viviana has also co-led the ST AI Affinity Team, coordinating a global community of more than 100 experts working to accelerate AI innovation across the company.
An inventor and co-inventor on nine international patents, Viviana has contributed to numerous research initiatives, industry collaborations, and national and international programs advancing AI and semiconductor innovation.
She is equally passionate about developing people, fostering cross-functional collaboration, and creating opportunities for women in technology. Through mentoring, leadership, and advocacy, she continues to foster the next generation of innovators while helping shape a more inclusive future for the engineering community.
Viviana D'Alto
Artificial Intelligence SW & Tools Research Director (SRA/SCIS)
STMicroelectronics

Yanfang Le
AMD
Yanfang Le
Principal Network Architect
AMD
Yanfang Le, Ph.D., is a Principal Network Architect at AMD specializing in AI networking, distributed systems, and high-performance networking technologies. She earned her Ph.D. in Computer Sciences from the University of Wisconsin–Madison in 2020 and has since become a recognized leader in the design of scalable networking solutions for next-generation AI and cloud infrastructure. Her work spans RDMA transport, congestion control, programmable hardware, collective communications, and performance optimization for large-scale distributed systems.
At AMD, Yanfang plays a key role in advancing networking technologies for large-scale AI deployments. She is a major contributor to the Ultra Ethernet Consortium (UEC), where she has helped architect innovative transport solutions for AI networking, including congestion management, multipath load balancing, packet loss recovery, and performance scalability. Her contributions have helped shape emerging standards and technologies for future AI data center networks.
Beyond her technical work, Yanfang has been an active leader in industry standards development. She previously served as Chair of the UEC Performance and Debug Working Group, leading cross-industry collaboration on benchmarking methodologies, performance characterization, and debugging frameworks for AI networking environments. Prior to joining AMD, she worked at Intel, where she contributed to RoCEv2 networking technologies and co-invented Back-to-Sender (BTS) and Source Flow Control, innovations that have influenced ongoing industry standardization efforts.
A recipient of the 2025 WISH Female Up & Comer Award, Yanfang is also a prolific researcher and inventor. She has authored more than 10 peer-reviewed publications, holds more than 10 patents, and has received multiple Best Paper Awards. She serves on the program committees of leading systems and networking conferences, including NSDI and EuroSys, and continues to help shape the future of AI and high-performance networking through technical innovation, industry leadership, and community engagement.
Yanfang Le
Principal Network Architect
AMD
Tech Speakers

Abhishikta Pandit
Meta
Abhishikta Pandit
Principal Silicon EDA Infrastructure Engineer
Meta
Abhishikta Pandit is a Principal Silicon EDA Infrastructure Engineer at Meta, leading architectural strategy across CAD infrastructure, design methodology, and advanced design flow development. Operating where design flows meet large-scale hardware pipelines, she defines how AI-native principles reshape core design and engineering workflows, driving innovation, compute efficiency, and velocity across next-generation silicon development. A champion of AI as a catalyst in engineering, Abhishikta holds a Master’s in Electrical Engineering from the University of Colorado Boulder.
Abhishikta Pandit
Principal Silicon EDA Infrastructure Engineer
Meta

Aradhana Kumari
STMicroelectronics
Aradhana Kumari
Staff Engineer in Research & Innovation Team
STMicroelectronics
Aradhana is a Staff Engineer in Research & Innovation Team at STMicroelectronics, Crolles, France. A digital design architect specializing in serial link controllers, low-power architectures, and high-performance die-to-die interfaces for heterogeneous chiplet systems. Recognized globally for her innovation and technical leadership, receiving the 2023 GSA WLI Female Up & Comer Award and the 2024 Special Achievement Award from MIPI Alliance. Aradhana holds 10 U.S. patents and has authored 18 publications in major international conferences.
Aradhana Kumari
Staff Engineer in Research & Innovation Team
STMicroelectronics

Cynara Justine
Microsoft
Cynara Justine
Senior Software Engineer
Microsoft
Cynara Justine is a Senior Software Engineer at Microsoft with 18 years of experience across AI, firmware engineering, and systems software. She previously worked in HP/HPE R&D, contributing to firmware, HPC, and AI systems. She holds a B.Tech. in Electronics and Communication Engineering, an M.S. in Software Systems, and has submitted her Ph.D. thesis in AI. A lifelong learner with 260+ certifications, she is an inventor with patents and focuses on federated learning, security, and privacy-preserving systems.
Cynara Justine
Senior Software Engineer
Microsoft

Jasmine Chang
Micron Technology
Jasmine Chang
Dry Etch Process Engineer
Micron Technology
Jasmine Chang is a Dry Etch Process Engineer at Micron Technology, contributing to advanced DRAM development since 2014. She has supported multiple technology nodes, including 1α, 1β, and 1γ, with a focus on EUV patterning and critical etch integration. Her work centers on developing scalable, manufacturable etch solutions and driving process innovation that accelerates technology development and enables high-volume manufacturing readiness. Her expertise spans advanced patterning integration, process optimization, and manufacturing execution for next-generation DRAM technologies.
Jasmine Chang
Dry Etch Process Engineer
Micron Technology

Irene Monica Lasar
STMicroelectronics
Irene Monica Lasar
Senior Technology Development Engineer
STMicroelectronics
Irene Monica Lasar is a Senior Technology Development Engineer at STMicroelectronics Singapore, where she has been contributing to Power MOSFET technology development since 2025. Her work focuses on bridging innovation and manufacturability to develop scalable technology solutions for low-voltage discrete devices. She earned her M.S. in Green Electronics (Microelectronics) through a joint program between Nanyang Technological University, Singapore, and the Technical University of Munich, Germany, in 2021.
Irene Monica Lasar
Senior Technology Development Engineer
STMicroelectronics

Lalitha Abraham
Synaptics
Lalitha Abraham
Principal Test Development Engineer
Synaptics
Lalitha Abraham is a Principal Test Development Engineer at Synaptics with over 25 years of semiconductor experience spanning process, product, and test engineering. She holds an MSEE from the University of Arkansas and an undergraduate degree in Electronics Engineering from the National Institute of Technology, India. Her work includes advanced semiconductor test solutions and developing DFT and testability guidelines across business units. She is committed to collaboration across engineering teams and mentoring the next generation of engineers.
Lalitha Abraham
Principal Test Development Engineer
Synaptics

Liya Liu
AMD
Liya Liu
Senior Member of Technical Staff
AMD
Dr. Liya Liu is a Senior Member of Technical Staff at AMD, with over 13 years of experience. Her work focuses on formal verification in Security IP and DV methodology exploration. Previously, she was a Research Assistant in Concordia University’s Hardware Verification Group, specializing in theorem proving. She earned her Ph.D. in 2013, an M.Eng from Concordia University, and an M.A.Sc from Wuhan Technical University of Surveying and Mapping.
Liya Liu
Senior Member of Technical Staff
AMD

Mrunal Sagare
Lattice Semiconductor
Mrunal Sagare
Physical Design Engineer
Lattice Semiconductor
Hi everyone, my name is Mrunal Sagare, and I am a Physical Design Engineer at Lattice Semiconductor. I completed my B.Tech in Electronics and Telecommunication Engineering from Savitribai Phule Pune University in May 2026. Prior to joining my current role, I completed a one-year internship at Lattice Semiconductor, where I gained hands-on experience in ASIC and FPGA design flows. My technical expertise includes Physical Design, PnR, STA, Physical Verification, EMIR analysis, and FPGA Design. I am particularly interested in timing closure, design optimization, and advanced implementation methodologies for high-performance semiconductor devices.
Mrunal Sagare
Physical Design Engineer
Lattice Semiconductor

Neetu Mehta
AMD
Neetu Mehta
Senior Silicon Design Engineer
AMD
Neetu is a Senior Silicon Design Engineer at AMD India with 9 years in the semiconductor industry, along with 2.5 years of teaching experience as an Assistant Professor. She began her career as a Physical Design Engineer at HCL Technologies, delivered complex SoC blocks across 16nm–7nm nodes for multiple successful SOC’s tape-outs, with expertise in physical design, timing closure, power optimization, multi-voltage implementation, and sign-off. At AMD, she works in CAD methodology for timing and power, driving flow development, enablement of new features, optimization, automation, and tool qualification for advanced nodes. She holds an M-Tech in Microelectronics & VLSI Design from Kurukshetra University and has authored a publication on Double Gate MOSFET simulation presented at an international conference in New Delhi. She won the IEEE Bangalore Section “Young Technologist of the Year 2025” Award for technical leadership and impact, plus multiple AMD Spotlight Awards and HCL’s ERS Champion’s Award for closing a challenging block on time with high efficiency.
Neetu Mehta
Senior Silicon Design Engineer
AMD

Nupur Bhonge
Amazon Web Services (AWS)
Nupur Bhonge
Solutions Architect
Amazon Web Services (AWS)
Nupur Bhonge is a Solutions Architect at Amazon Web Services, where she helps hi-tech and semiconductor enterprise customers design and scale cloud solutions. Her work focuses on applying AI and multi-agent systems to hardware design and verification workflows, including automated root-cause analysis for RTL verification. She is passionate about bridging cloud technology and semiconductor engineering to accelerate innovation and improve productivity across the chip design lifecycle.
Nupur Bhonge
Solutions Architect
Amazon Web Services (AWS)

Pallavi Atha
Astera Labs
Pallavi Atha
Principal Formal Verification Engineering Manager
Astera Labs
Pallavi Atha is a Technology Leader with 14+ years of experience in SoC design verification , specializing in formal verification and product engineering in semiconductor Industry . Her expertise spans verification strategy, formal methodologies, coverage, proof convergence, and verification automation for complex hardware designs. Her work focuses on applying generative and agentic AI to transform verification workflows, improve engineering productivity, and address scalability challenges in modern SoC development. She is passionate about advancing innovative verification methodologies and enabling reliable, high-quality hardware systems.
Pallavi Atha
Principal Formal Verification Engineering Manager
Astera Labs

Rajashri Lakhotia
Lattice Semiconductor
Rajashri Lakhotia
Senior Staff Manager
Lattice Semiconductor
Rajashri is a Senior Staff Manager at Lattice Semiconductor with nearly two decades of experience in physical design and integration. She leads a physical design team, driving complex SoC design closure across technology nodes. Her career spans roles at Marvell and STMicroelectronics, and she has a strong track record of managing teams globally and delivering many tape outs and projects successfully. She holds a Bachelor of Engineering from Pune University and is passionate about design, technology, process, quality, and semiconductor reliability.
Outside of her technical role, she enjoys traveling and exploring the financial markets, and lives in Pune, India, with her husband and two teenage children.
Rajashri Lakhotia
Senior Staff Manager
Lattice Semiconductor

Sara Bourouga
STMicroelectronics
Sara Bourouga
Technical Marketing & Application Support Engineer, EMEA Automotive
STMicroelectronics
Sara Bourouga is a Technical Marketing & Application Support Engineer at STMicroelectronics’ EMEA Automotive organization, specializing in automotive power electronics, including Si/SiC MOSFETs, IGBTs, GaN devices, and high-voltage gate drivers. Her work spans on-board chargers, DC-DC converters, inverters, and intelligent power systems. She has contributed to publications on OBC architectures, power conversion, and semiconductor thermal management, co-invented a single-stage AC/DC OBC control method, and presented on power electronics for AI-driven robotics.
Sara Bourouga
Technical Marketing & Application Support Engineer, EMEA Automotive
STMicroelectronics

Sindhu Amireddy
Microsoft
Sindhu Amireddy
Principal SoC Architect
Microsoft
Sindhu Amireddy is a Principal SoC Architect at Microsoft, where she helps define the architecture of next-generation processors powering Azure cloud infrastructure. With over a decade of experience across Microsoft and Intel, she has led architecture and integration initiatives spanning hardware-firmware interfaces, system integration, and silicon bring-up. Her current work focuses on boot, reset, and interrupt architectures for complex chipletbased systems. Sindhu is passionate about turning complex architectural concepts into clear specifications and shared architectural frameworks that help hardware and firmware teams align, integrate, and deliver high-quality silicon.
Sindhu Amireddy
Principal SoC Architect
Microsoft

Smitha Kashyap C
Microsoft
Smitha Kashyap C
Principal Systems Engineer
Microsoft
Smitha Kashyap C is a Principal Systems Engineer at Microsoft with 20+ years of experience in Hardware System Engineering, Platform Validation, and Cloud Infrastructure. She leads large-scale validation programs for hyperscale datacentres, with a focus on sustainability, reliability, and AI-driven engineering. Smitha is an inventor, mentor, and advocate for women in technology and industry leadership.
Smitha Kashyap C
Principal Systems Engineer
Microsoft

Susan Li
Marvell Technology
Susan Li
Technical Director of Failure Analysis
Marvell Technology
Susan Li is Technical Director of Failure Analysis at Marvell Technology, developing advanced tools and techniques for cutting-edge technology nodes and 2.5D/3D advanced packaging. Worked at AMD/Spansion/Cypress/Infineon, and now Marvell to support a wide range of IC products. Has a Master’s in Materials Science and Engineering from Carnegie Mellon University in the US and a Bachelor’s in Electronics Engineering from Peking University in China. Published over 30 papers at international conferences and holds 21 US patents.
Susan Li
Technical Director of Failure Analysis
Marvell Technology

Tala Sidawi
Ayar Labs
Tala Sidawi
Senior Product Reliability Engineer
Ayar Labs
Tala Sidawi earned her B.S. in Environmental Engineering from the University of Georgia and an M.S. in Nanoengineering from UC San Diego. Since joining Ayar Labs in 2022, she has helped establish and scale critical reliability methodologies for the deployment of next-generation SiPh technology in AI computing systems. Her work spans reliability testing, automation, modeling reliability risks, standardizing testing data structure, and cross-functional collaboration with design and test teams to enable product qualification and manufacturing readiness.
Tala Sidawi
Senior Product Reliability Engineer
Ayar Labs

Vidya Samyuktha
Microsoft
Vidya Samyuktha
Principal Hardware Systems Engineer
Microsoft
Vidya Samyuktha is a Principal Hardware Systems Engineer at Microsoft, driving End-to-End Validation and platform enablement for next-generation Azure Server Hardware. Her expertise includes system architecture, silicon bring-up, hardware-software integration, and accelerator technologies. Beyond technical leadership, she is committed to fostering collaboration across teams and helping engineers navigate complex technical challenges, enabling the delivery of scalable, reliable solutions that strengthen cloud infrastructure and enhance customer experiences worldwide.
Vidya Samyuktha
Principal Hardware Systems Engineer
Microsoft
Sponsors
Title Sponsor
Title Sponsor
Marvell delivers accelerated infrastructure solutions that move, process, store, and secure the world’s data. As a leader in semiconductor technology, we power innovation in AI, cloud, carrier infrastructure, enterprise networking, and data centers. Our portfolio spans custom compute, interconnects, network switching, and storage. With decades of expertise in architecture, design IP, silicon services, and packaging, Marvell provides end-to-end cloud solutions that enable hyperscalers to deploy tailored AI infrastructure for any application.
VIP Reception Sponsor
VIP Reception Sponsor
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and advanced packaging technology leadership. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of industry-leading technology, a rich IP portfolio, a world-class design ecosystem, in-house acceleration services and an operationally resilient global manufacturing supply chain.
Lunch Sponsor
Lunch Sponsor
TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since.
The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry.
With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
Photobooth Sponsor
Photobooth Sponsor
Credo is an innovator in providing connectivity at scale through fast, reliable, and energy-efficient system solutions for the next generation of AI-driven applications, cloud computing, and hyperscale networks. We provide state-of-the-art solutions for the most demanding connectivity needs, supporting data rates up to 1.6T across a range of industry protocols.
Rising Women in Semi Award Sponsor
Rising Women in Semi Award Sponsor
At Sandisk, we keep people and businesses moving forward with inspired innovations to actualize their potential. Our vast portfolio of Flash products enables a seamless and simplified world of resilient data expression and storage. We believe that everyone should be inspired by their data – to move, create, discover, share, and unlock their potential.
Female Up and Comer Award Sponsor
Female Up and Comer Award Sponsor
AMD is the high performance and adaptive computing leader, powering the products and services that help solve the world’s most important challenges. Our technologies advance the future of the data center, embedded, gaming and PC markets.
Founded in 1969 as a Silicon Valley start-up, the AMD journey began with dozens of employees who were passionate about creating leading-edge semiconductor products. AMD has grown into a global company setting the standard for modern computing, with many important industry firsts and major technological achievements along the way.
Designing the Difference Award Sponsor
Designing the Difference Award Sponsor
The landscape of technology is constantly evolving, making it challenging to stay on top of trends and maintain field-level expertise. Our labs provide the essential day-to-day knowledge and experience required to develop cutting-edge solutions in the AI space. We’re here to assist you in navigating the complexities and hurdles on your journey, from concept to market.
Wellness Break Sponsor
Wellness Break Sponsor
Samsung Semiconductor is a global technology leader in memory, logic, and foundry solutions that power today’s most advanced enterprise and mobile technologies. From AI and data analytics to servers, storage, and next-gen infrastructure, our high-performance semiconductors enable customers to accelerate digital transformation. In close collaboration with our customers and partners, Samsung drives innovation across data centers, edge computing, and AI workloads—delivering the speed, capacity, and intelligence the modern world demands.
VIP Dinner Sponsor
VIP Dinner Sponsor
We’re driven to build incredible things that connect people in inspiring ways. Because we can’t truly advance groundbreaking AI alone, we share our research and engage with the AI community to advance the science, together. Whether it be in AI Infrastructure, Generative AI, NLP, Computer Vision or other core areas of AI, our focus is to connect people in inspiring ways through collaborative, responsible AI innovation.
Breakfast Sponsor
Breakfast Sponsor
Siemens EDA provides a comprehensive portfolio of electronic design automation (EDA) software, hardware, and services for the design, verification and manufacturing of integrated circuits (ICs) and electronic systems. What’s more, Siemens is breaking down the barriers between electrical, mechanical and software design disciplines, between design and manufacturing, bridging virtual and physical design and manufacturing, enabling companies to rapidly advance in their digital transformation and evolve from systems to market-leading ecosystems companies with the Siemens Xcelerator portfolio. For more information on Siemens EDA products and services, visit siemens.com/eda.
Dessert Bar Sponsor
Dessert Bar Sponsor
Coherent is the global photonics leader. We harness photons to drive innovation. Industry leaders in the datacenter, communications, and industrial markets rely on Coherent’s world-leading technology to fuel their own innovation and growth.
Founded in 1971 and operating in more than 20 countries, Coherent brings the industry’s broadest, deepest technology stack; unmatched supply chain resilience; and global scale to help its customers solve their toughest technology challenges.
Wi-Fi Sponsor
Wi-Fi Sponsor
At Lam, our mission is to drive semiconductor breakthroughs that define the next generation.
Our Mission speaks to what we do – Lam is a technology-first company. We are about driving the next technology breakthrough for the semiconductor industry. We think bigger on the game-changing innovations that will define the next generation of technology.
Wishing Wall Sponsor
Wishing Wall Sponsor
Ayar Labs is transforming AI infrastructure by accelerating data movement. Our breakthrough optical I/O solution enables composable system architectures optimized for large-scale AI workloads, while also scaling performance and throughput for training and inference. Ayar Labs’ industry-first, standards-based technology shatters data bottlenecks and gives customers the bandwidth, energy efficiency, and latency that AI workloads require.
Charging Station Sponsor
Charging Station Sponsor
Cisco is the worldwide technology leader that securely connects everything to make anything possible. Our purpose is to power an inclusive future for all by helping our customers reimagine their applications, power hybrid work, secure their enterprise, transform their infrastructure, and meet their sustainability goals.
Virtual Booklet Sponsor
Virtual Booklet Sponsor
Power Integrations, Inc., is a leading innovator in semiconductor technologies for high-voltage power conversion. Our products are key building blocks in the clean-power ecosystem, enabling the generation of renewable energy as well as the efficient transmission and consumption of power in a vast range of applications including appliances, mobile devices, computers and countless industrial applications.
Coffee Station Sponsor
Coffee Station Sponsor
Astera Labs is a global leader in purpose-built connectivity solutions for rack-scale AI,
pioneering software-defined architecture that is scalable and customizable.
Our portfolio includes PCIe®, CXL®, Ethernet, UALink™, and NVLink Fusion semiconductor-based solutions to solve data, memory, and networking bottlenecks. Our work centers around trusted relationships with hyperscalers and the data center ecosystem.
Smoothie Break Sponsor
Smoothie Break Sponsor
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics.
In 2026, Cadence was recognized by Fortune as one of the world’s top 100 best companies to work for. Cadence solutions offer limitless opportunities.
Platinum Sponsor
Platinum Sponsor
We are the leader in materials engineering solutions that are at the foundation of virtually every new semiconductor and advanced display in the world. The solutions we create are essential to advancing AI and accelerating the commercialization of next-generation chips.
For more than 55 years, our innovations have improved the lives of billions of people around the globe who may never know us by name, but who rely on us every day as they interact with technology.
The world’s brightest minds—visionaries, engineers, scientists—bring their expertise in materials engineering and come together at Applied with a collection of diverse opinions, experiences and backgrounds.
Gold Sponsor
Gold Sponsor
Infineon Technologies AG is a global semiconductor leader in power systems and IoT. Infineon drives decarbonization and digitalization with its products and solutions. The Company had around 57,000 employees worldwide (end of September 2025) and generated revenue of about €14.7 billion in the 2025 fiscal year (ending 30 September). Infineon is listed on the Frankfurt Stock Exchange (ticker symbol: IFX) and in the USA on the OTCQX International over-the-counter market (ticker symbol: IFNNY).
Gold Sponsor
Gold Sponsor
We are a world leader in innovative memory solutions that transform how the world uses information to enrich life for all. For over 45 years, our company has been instrumental to the world’s most significant technology advancements, delivering optimal memory and storage systems for a broad range of applications.
Gold Sponsor
Gold Sponsor
At ST, we are creators and makers of semiconductor technologies mastering the semiconductor supply chain with state-of-the-art manufacturing facilities. As an integrated device manufacturer, we work with our customers and partners to design and build products, solutions, and ecosystems that address their challenges and opportunities, and the need to support a more sustainable world. Our technologies enable smarter mobility, more efficient power and energy management, and the wide-scale deployment of cloud-connected autonomous things.
Gold Sponsor
Gold Sponsor
Teradyne designs, develops, and manufactures automated test equipment and advanced robotics systems. Its test solutions for semiconductors and electronics products enable Teradyne’s customers to consistently deliver on their quality standards. Its advanced robotics business includes collaborative robots and mobile robots that support manufacturing and warehouse operations for companies of all sizes. For more information, visit teradyne.com.
General Sponsor
General Sponsor
Since our founding in 2015, Cerebras has consistently innovated at the edge of what’s possible in AI computing.
Today, Cerebras stands alone as the world’s fastest AI inference and training platform. Organizations across fields like medical research, cryptography, energy, and agentic AI use our CS-2 and CS-3 systems to build on-premise supercomputers, while developers and enterprises everywhere can access the power of Cerebras through our pay-as-you-go cloud offerings.
We have come a long way in our first decade. But our journey is just beginning.
General Sponsor
General Sponsor
Industry leaders are looking to Emerson as a trusted partner that continuously innovates to help them meet the next big challenge. Our robust automation portfolio enables us to collaborate across our businesses to develop more complete solutions for customers based on our deep industry experience. We leverage our global presence, domain expertise and industrial software to help industries achieve key sustainability and operational goals.
General Sponsor
General Sponsor
General Sponsor
General Sponsor
GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, power‑efficient and high‑performance solutions for automotive, aerospace and defense, data center, smart mobile devices, internet of things and other high‑growth markets. With global manufacturing operations across the U.S., Europe and Asia, GF is a trusted and holistic technology partner for customers around the world. GF’s talented, global team remains focused every day on security, longevity and sustainability. For more information, visit www.gf.com.
General Sponsor
General Sponsor
Imec is a global semiconductor R&D center that drives the roadmap for the hardware that will power tomorrow’s AI‑driven era.
Imec pioneers chip innovation, scales it through venturing, and brings it to the real world through global collaboration. For over 40 years, we have united the semiconductor ecosystem around a unique, state‑of‑the‑art R&D infrastructure. Here, companies collaborate on common ground to tackle shared technology challenges and create tangible impact for industry and society. Together, we are shaping how people live, work, move, learn and stay healthy.
At imec we don’t just imagine the future. We build it.
Event Survey Sponsor
Event Survey Sponsor
Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.
Awards
Dr. Lisa Su Woman of Innovation Award
The Woman of Innovation Award recognizes an industry veteran who has dedicated her career to making exceptional contributions to drive the development, innovation, growth and long-term opportunities for the semiconductor industry.
Winner

Debora Shoquist
NVIDIA
Debora Shoquist
EVP of Operations
NVIDIA
Debora Shoquist is executive vice president of operations at NVIDIA. She is responsible for the company’s operations and supply chain functions. These include manufacturing product and test engineering, foundry operations, supplier management and contract-manufacturing management, supply planning, logistics, and the company’s quality management system. She was also responsible for overseeing construction of the company’s new 1.25 million-square-foot corporate headquarters in Santa Clara, Calif.
Shoquist joined NVIDIA in 2007 as senior vice president of operations and was named to her current role two years later. She has more than 20 years of executive experience in general management, manufacturing and operations, including plant management, engineering, information services, finance and human resources.
Previously, Shoquist was executive vice president of operations at JDS Uniphase and senior vice president and general manager of the electro-optics business at Coherent, a manufacturer of commercial and scientific laser equipment. She also spent 11 years in key executive roles at Quantum, including president of the Personal Computer Hard Disk Drive division, and 10 years at HP in various engineering and manufacturing management roles.
Shoquist holds a Bachelor of Science in electrical engineering from Kansas State University and a Bachelor of Science in biology from Santa Clara University.
EVP of Operations
Female Up and Comer Award
The Female Up and Comer Award recognizes and profiles the next generation of young women in the semiconductor industry. Companies are encouraged to identify women with a technical background and education within their organization who have been in the industry five years or less and have made exceptional contributions toward the development, innovation, growth and success in her short time in the industry.
Rising Women in Semi Award
The GSA Rising Women in Semi Award will recognize three to four female nominees who are considered rising leaders by their individual companies. These nominees should have made exceptional contributions toward the development, innovation, growth, and success of the semiconductor industry and made a huge impact during her time in the industry, which should be more than ten years but less than twenty years.
Designing the Difference Award
The Designing the Difference Award recognizes a semiconductor company that has taken intentional, measurable steps to create an environment where innovation and diverse perspectives are valued and contribute to a forward-thinking industry. Companies should demonstrate company-wide initiatives, internal culture, community engagement and overall commitment to creating an environment where innovation and diverse perspectives are valued and contribute to industry impact and overall long-term vision of meaningful leadership and culture.
Posters
AI-Augmented Manufacturing Analytics: Eliminating the Data Bottleneck in HSIO Test Failure Correlation

Manvitha Pannala
AMD
Manvitha Pannala
Senior Silicon Design Engineer
AMD
Manvitha is a Senior Silicon Design Engineer at AMD, currently serving as the Data Analyst for Data Center GPU HSIO Validation. In this role, she leads AI-driven data analytics approaches integrating cloud data platforms such as Snowflake and Databricks across critical IP blocks. Prior to this, Manvitha was the Technical Program Manager, focusing on the cross-functional efforts to drive silicon design execution and program alignment. And she was the technical lead for third-party security IPs, including AEMC, and was responsible for the development and power integrity verification of third-party IPs such as multiple generations of USB and PCIe.
With approximately five years of experience in the semiconductor industry, she began her career at Intel, before joining AMD in 2022. Manvitha holds a master’s degree (Thesis) in Electrical Engineering from Arizona State University. Outside of work, she enjoys traveling, cooking, sketching, and spending quality time with her family.
Manvitha Pannala
AMD
Safety Verification of Complex SoCs: “Fault Detection, Collection and Reaction” to maintain SoC in safe state

Anamika Sharma
STMicroelectronics
Anamika Sharma
STMicroelectronics
With 14 years of industry experience, including 12 years at STMicroelectronics, I have led verification of Safety, ADC Subsystem, NoC, and AES for automotive products. I established automation frameworks and verification tracking methodologies for SoC programs . I am also leading IP and SoC-level verification of various IPs. As a key member of the India SoC Verification team, I contribute to delivering reliable, high-quality semiconductor solutions through technical expertise, leadership, and rigorous verification practices.
Anamika Sharma
STMicroelectronics
Improving RTL Power Predictability Through Architecture-Level Estimation Modeling

Chiew Shu Tan
Lattice Semiconductor
Chiew Shu Tan
Senior Manager, Design Engineering
Lattice Semiconductor
Chiew Shu Tan is a Senior Manager of Design Engineering at Lattice Semiconductor with over 15 years of experience in ASIC and FPGA technologies. She leads global teams developing advanced high-speed serial interface and programmable device solutions while driving innovation through verification methodology advancement, intellectual property development, and cross-functional collaboration. Passionate about technical excellence and engineering leadership, she actively contributes to semiconductor innovation, talent development, and organizational growth.
Chiew Shu Tan
Lattice Semiconductor
Adaptive Storage Device with Intent-Aware Operational Modes

N Varshitha
SanDisk
N Varshitha
Product Validation Engineer
SanDisk
N Varshitha is a Product Validation Engineer at SanDisk working on consumer flash storage products. She develops validation frameworks and test solutions that enable reliable product qualification while providing deeper visibility into product behavior. Leveraging strong expertise in storage protocols and system-level debugging, Varshitha investigates complex failures, drives root-cause analysis, and builds scalable tools that automate failure characterization. Her work focuses on advancing validation efficiency, product quality, and data-driven engineering workflows.
N Varshitha
SanDisk
Wire Bond Application Extended to 800G Coherent Optical Module

Nelly Chase
Marvell
Nelly Chase
Senior Staff Engineer
Marvell
Nelly Chase is a Senior Staff Engineer at Marvell Technology specializing in advanced semiconductor packaging and silicon photonics. She earned her Ph.D. in Materials Science from UCLA, where her research focused on heterogeneous integration, silicon-based substrates, non-organic passivation, and package reliability. At Marvell, she develops advanced packaging solutions for next-generation silicon photonic products, with expertise in Near-Packaged Optics (NPO), Co-Packaged Optics (CPO), and high-performance optical interconnect technologies.
Nelly Chase
Marvell
HASA-Net: Hardware-Aware Spatial Attention Network for Edge-Efficient Brain Tumor Segmentation

Somayeh Davar
Concordia University
Somayeh Davar
Ph.D. Candidate Computer Science
Concordia University
Somayeh is a Ph.D. candidate in Computer Science at Concordia University, specializing in artificial intelligence, computer vision, and deep learning for biomedical and healthcare applications. Her research focuses on efficient AI methods for medical image analysis, including tumor detection and segmentation, with growing emphasis on hardware-aware and clinically deployable AI. She is an FRQNT doctoral scholarship recipient and a Borealis AI Fellowship recipient, recognizing her research contributions in AI and machine learning.
Somayeh Davar
Concordia University
Agentic PCIe Retimer LTSSM Log Analysis with Recursive Improvement

Aditi Narayan Prasad
Astera Labs
Aditi Narayan Prasad
Applied AI Engineer
Astera Labs
Aditi Narayan Prasad
Astera Labs
Beyond the Die: AI-Driven End-to-End Verification of Multi-Die Systems

Sridevi Jagata
Cadence
Sridevi Jagata
Lead Application Engineer
Cadence
I am a Lead Application Engineer specializing in system-level and protocol verification for complex SoC and IP designs. My deep technical expertise spans PCIe, CXL, AMBA CHI, Portable Stimulus (PSS), UVM, and verification IP methodologies.
I work on deploying scalable verification solutions across simulation and emulation environments, focusing on protocol validation, coherency verification, traffic modeling, debug, and automation.
I also drive customer enablement, methodology adoption, and development of reusable verification solutions that accelerate verification closure and improve overall SoC quality and reliability.
Sridevi Jagata
Cadence
Split-Gate Inter-Poly Architecture for Electrical Gate Leakage and Mechanical Wafer Warpage Optimization in Trench FP-MOSFETs

Irene Monica Lasar
STMicroelectronics
Irene Monica Lasar
Senior Technology Development Engineer
STMicroelectronics
Irene Monica Lasar is a Senior Technology Development Engineer at STMicroelectronics Singapore, where she has been contributing to Power MOSFET technology development since 2025. Her work focuses on bridging innovation and manufacturability to develop scalable technology solutions for low-voltage discrete devices. She earned her M.S. in Green Electronics (Microelectronics) through a joint program between Nanyang Technological University, Singapore, and the Technical University of Munich, Germany, in 2021.
Irene Monica Lasar
STMicroelectronics
Workload-Aware and Interaction-Driven Validation of Enterprise SSDs for AI Infrastructure

Kavita Sradhana
Sandisk
Kavita Sradhana
Staff Engineer
Sandisk
Kavita Sradhana is a Staff Engineer at Sandisk with over nine years of experience in storage technologies, including NVMe, PCIe, and SSD firmware. Holding a Master’s degree in Computer Science, she combines deep technical expertise with a passion for innovation, research, and knowledge sharing. She is actively engaged in technical publications and intellectual property development in storage domain. Outside work, she enjoys traveling, exploring new cultures, and drawing inspiration from diverse experiences and perspectives.
Kavita Sradhana
Sandisk
System-Level Datatcenter Telemetry Collection

Maya Subhadra
Microsoft
Maya Subhadra
Principal Architect
Microsoft
Maya Subhadra is a Principal Architect at Microsoft, driving system architecture and
innovation for next-generation Azure silicon platforms. With more than 20 years of
experience across Microsoft and Intel, she is known for solving complex challenges in
chiplet architectures, system counter synchronization, power management, and scalable
control plane infrastructure. Maya’s work spans the full silicon lifecycle, from architecture
definition through RTL, verification, firmware enablement, and post-silicon debug, helping
deliver the next generation of cloud infrastructure.
Maya Subhadra
Microsoft
A Capability-Based Framework for OSAT Selection for Thermo-Compression Bonding in Advanced Semiconductor Packaging

Neha Saste
Marvell
Neha Saste
Advanced Packaging and Process Integration Engineer
Marvell
Neha Saste is an Advanced Packaging and Process Integration Engineer with 6+ years of experience, including 4.5 years at Intel and currently at Marvell. Her expertise spans TCB, 2.5D/3D heterogeneous integration, chiplets, HBM integration, fine-pitch interconnects, advanced assembly, process integration, yield optimization, failure analysis, and OSAT manufacturing. Her work focuses on developing robust, scalable advanced packaging technologies for next-generation AI and HPC products.
Neha Saste
Marvell
Broadening BSI CMOS Pixel Response from Visible to UV Light

Nour Fassi
STMicroelectronics
Nour Fassi
Electro-optical Characterization Engineer
STMicroelectronics
Nour Fassi is an Electro-optical Characterization Engineer at STMicroelectronics Edinburgh and an embedded systems engineer by training. Her work spans image sensors, ALS, and SPAD technologies, covering characterization, qualification, and optical research from experimental setup to data analysis. She holds a PhD in photonics and optoelectronics from ISAE-SUPAERO, University of Toulouse, where she focused on investigating ultraviolet sensitivity in backside-illuminated CMOS pixels. She is also active in STEM outreach and education-access initiatives
Nour Fassi
STMicroelectronics
ECO FILL: An Optimized Approach to Metal Fill Insertion for Handling ECOs

Priyanka Inani
Cisco
Priyanka Inani
Senior Semiconductor Physical Verification Engineer
Cisco
Priyanka Inani is a Senior Semiconductor Physical Verification Engineer at Cisco Systems. Holding a master’s degree in computer engineering with deep VLSI design expertise, she specializes in advanced integrated circuit layout, chip architecture, and complex sign-off execution. Drawing on extensive experience from top technology firms including Intel, she leads physical design verification, and cross-functional hardware enablement to power next-generation silicon devices. Off the clock, she enjoys dance, acting, cooking, and spending time with her family.
Priyanka Inani
Cisco
Productionizing Integrated AI Hardware Systems at Meta Fleet Scale

Salina Dbritto
Meta
Salina Dbritto
AI Systems Engineer
Meta
Salina is an AI Systems Engineer at Meta with over 12 years of industry experience, leading efforts to validate and scale integrated AI systems from early development through fleet scale. Working on MTIA (Meta Training and Inference Accelerators), she champions a whole-system view across networking, compute, and silicon — leading rack-level integration to reduce job interruptions and raise diagnostic accuracy for reliable AI at scale. She also leads automation frameworks and tooling that keep systems healthy. Beyond tech, Salina loves public speaking, singing, and event hosting.
Salina Dbritto
Meta
Integrated SSD with KV Cache, nCache, TLC/SLC for the AI solutions

Vedavathi Koguru
Sandisk
Vedavathi Koguru
Senior Product Validation Engineer
Sandisk
Vedavathi Koguruis a Senior Product Validation Engineer at Sandisk, with over 15 years of experience in embedded and storage technologies. She holds a Master’s degree in Embedded Systems Design and a Bachelor’s degree in Electronics. Her expertise includes enterprise and automotive SSD validation, AI-driven validation solutions, and intelligent automation with AI agents for the day-to-day validation tasks. Passionate about innovation and research, she focuses on AI-enabled storage architectures, and next-generation storage technologies that improve system efficiency, performance, and scalability.
Vedavathi Koguru
Sandisk
Left-Shift PDK Evaluation: A Unified Framework for Predictive Cross-Technology Scaling and Device Characterization

Sana
Sandisk
Sana
ASIC Methodology Engineer
Sandisk
Sana is an ASIC Methodology Engineer at Sandisk Corporation, Bengaluru, India, with 4.5 years of experience in the Analog CAD domain. She holds a Master’s degree in VLSI Design Engineering and specializes in developing innovative automation methodologies for layout design, physical verification checks, and EMIR flows. Her work focuses on building efficient, scalable solutions that streamline analog workflows, strengthen design validation, improve productivity, and accelerate the design cycle.
Sana
Sandisk
At the Limits of Power and Packaging: Rethinking Package-Level Production Burn-In for Next-Generation AI Accelerators

Sujata Paul
Microsoft
Sujata Paul
Silicon Reliability Engineer
Microsoft
Sujata is a silicon reliability engineer and technologist specializing in the qualification of advanced compute and AI accelerators. With a Ph.D. in Physics from North Carolina State University and more than a decade of experience at IBM, Cisco, Marvell, and Microsoft, she brings a broad perspective spanning device physics, component reliability, data-center optics, advanced packaging, and system-level validation.
Driven by curiosity and continuous learning, Sujata is passionate about technology, innovation, quality, semiconductor and optics reliability. She enjoys translating complex reliability challenges into practical engineering solutions. She lives in Fremont, California, with her husband and teenage son and enjoys cooking, traveling, and reading.
Sujata Paul
Microsoft
Custom-Trained LLMs for Semiconductor Domain Specific Languages: Overcoming the DSL Performance Ceiling Through Strategic Model Engineering

Dhara Vaishnav
Quantum Fab, AWS
Dhara Vaishnav
Head of Solution Architecture
Quantum Fab, AWS
Dhara Vaishnav brings over twenty years of experience building high-performance engineering teams to her role leading Solution Architecture for AWS’s Semiconductor and Quantum Fab practice. Passionate about harnessing diverse perspectives to deliver high-impact, purpose-driven solutions, she pioneers agentic AI applications for the semiconductor ecosystem and leads strategic model engineering efforts to advance LLM performance on the domain-specific languages that underpin chip design, verification, and manufacturing.
Dhara Vaishnav
Quantum Fab, AWS
Pricing
Standard Rate
Member
$199
Guests
$349
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Travel

Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054 United States
Hyatt Regency Santa Clara
Avatar Hotel Santa Clara
DoubleTree by Hilton Hotel San Jose
Student tickets are available at a discounted rate of $35. To secure a student ticket, please reach out to events@gsaglobal.org.
To learn more about sponsoring, click the button below for availability.